本文關(guān)鍵詞： 混合基FFT 低復(fù)雜度 可配置蝶形單元 實(shí)時性 并行流水　出處：《北京理工大學(xué)》2014年博士論文　論文類型：學(xué)位論文

【摘要】：快速傅里葉變換（Fast Fourier Transform, FFT）算法是雷達(dá)微波探測、通信及圖像等領(lǐng)域的核心處理算法，也是相關(guān)處理算法中運(yùn)算量較大的部分。但針對合成孔徑雷達(dá)（Synthetic Aperture Radar, SAR）以及正交頻分復(fù)用技術(shù)（Orthogonal FrequencyDivision Multiplexing, OFDM）應(yīng)用，現(xiàn)有FFT數(shù)字處理實(shí)現(xiàn)方法存在處理長度不靈活、處理器資源浪費(fèi)嚴(yán)重、處理延遲大等問題。因此，研究資源節(jié)約、高時效的低復(fù)雜度混合基FFT設(shè)計技術(shù)具有重要的應(yīng)用價值。本文通過對各種FFT算法進(jìn)行分析比較，提出了低復(fù)雜度混合基FFT設(shè)計方法。首先研究了基本蝶形單元的硬件實(shí)現(xiàn)方法，在此基礎(chǔ)上，研究了混合基FFT的低復(fù)雜度設(shè)計方法以及基于多存儲結(jié)構(gòu)的FFT設(shè)計方法。上述研究方法降低了FFT算法在數(shù)字電路中實(shí)現(xiàn)的復(fù)雜度，提高了FFT處理的實(shí)時性。主要工作和創(chuàng)新成果如下： 1.作為混合基FFT的一種特例，有必要對固定基FFT進(jìn)行研究�，F(xiàn)有FFT實(shí)現(xiàn)方法通常采用補(bǔ)零方式來滿足基-2或基-4FFT，該方法的不足之處在于浪費(fèi)存儲資源、計算時間長。針對這一問題，研究了基于單精度浮點(diǎn)運(yùn)算的以基-3和基-5蝶形單元為代表的小面積基-rFFT設(shè)計方法。同時，為了減少占用的存儲資源，在保證精度的前提下用定點(diǎn)格式來表示旋轉(zhuǎn)因子，設(shè)計了一種有效的、高精度的乘法器，以達(dá)到定點(diǎn)存儲旋轉(zhuǎn)因子的目的。 2.針對基-rFFT僅限于點(diǎn)數(shù)為r的冪次方的情況，提出了基于原位存儲結(jié)構(gòu)的混合基FFT設(shè)計。首先研究了基-r1/r2FFT數(shù)據(jù)訪問地址的生成方案，該方法通過一個計數(shù)器來獲得一種低復(fù)雜度的地址映射關(guān)系。進(jìn)一步推導(dǎo)通用混合基，即基-r1/r2/.../rsFFT數(shù)據(jù)訪問地址的產(chǎn)生方案。針對混合基FFT中蝶形單元種類增多的問題，推導(dǎo)出一種可配置的蝶形單元設(shè)計方法，解決了多種蝶形占用大量資源的問題。 3.針對原位存儲結(jié)構(gòu)實(shí)時性差這一問題，研究了基于多存儲結(jié)構(gòu)的混合基FFT實(shí)現(xiàn)方法。在兩種情況下進(jìn)行了討論：(a)單蝶形處理單元：給出了最優(yōu)的存儲器數(shù)目設(shè)置、優(yōu)化的數(shù)據(jù)分配方法以及對多個存儲空間的“并行流水”訪問方式；(b)多蝶形處理單元：研究了蝶形單元的數(shù)目設(shè)置以及對多個蝶形單元和多個存儲空間的結(jié)構(gòu)設(shè)計。該方案提高了混合基FFT的處理速度。
[Abstract]:Fast Fourier transform (FFTT) algorithm is the core processing algorithm of radar microwave detection, communication and image. It is also a part of the correlation processing algorithm, but it is aimed at synthetic Aperture Radar of synthetic Aperture Radar (SAR). And orthogonal FrequencyDivision Multiplexing (OFDM). The existing implementation methods of FFT digital processing have some problems, such as processing length is not flexible, processor resource is wasted seriously, processing delay is large, and so on. High-aging and low-complexity hybrid FFT design technology has important application value. This paper analyzes and compares various FFT algorithms. A low complexity hybrid base FFT design method is proposed. Firstly, the hardware implementation method of the basic butterfly unit is studied. The low complexity design method of hybrid base FFT and the design method of FFT based on multi-storage structure are studied. These methods reduce the complexity of FFT algorithm in digital circuits. The real-time performance of FFT processing is improved. The main work and innovative results are as follows: 1. As a special case of mixed radix FFT, it is necessary to study fixed base FFT, which is usually implemented by adding zero to satisfy radix-2 or radix-4FFT. The disadvantage of this method is that it wastes storage resources and takes a long time to calculate. This paper studies the design method of small area radix-rFFT based on single-precision floating-point operation, which is represented by radix--3 and radix-5 butterfly units. At the same time, in order to reduce the consumption of storage resources. On the premise of ensuring precision, the rotation factor is represented by fixed point format, and an effective and high precision multiplier is designed to store rotation factor at fixed point. 2. For the case that radix-rFFT is limited to the power power of the point r. A hybrid base FFT design based on in-situ storage structure is proposed. Firstly, the data access address generation scheme of radix-r-1 / r2FFT is studied. In this method, a low complexity address mapping relation is obtained by a counter, and the general mixed basis is further derived. In order to solve the problem of increasing the types of butterfly units in mixed radix FFT, a configurable design method of butterfly units is derived. It solves the problem that many kinds of butterfly take up a lot of resources. 3. Aiming at the problem of poor real-time performance of in-situ storage structure. In this paper, a hybrid base FFT implementation method based on multi-memory structure is studied. In two cases, the single butterfly processing unit is discussed: the optimal memory number setting is given. Optimized data allocation method and "parallel income" access to multiple storage spaces; (B) Multi-butterfly processing units: the number of butterfly units and the structural design of multiple butterfly cells and multiple storage spaces are studied. This scheme improves the processing speed of mixed base FFT.
【學(xué)位授予單位】：北京理工大學(xué)
【學(xué)位級別】：博士
【學(xué)位授予年份】：2014
【分類號】：TN911.7

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