本文關(guān)鍵詞：星載柔性轉(zhuǎn)發(fā)器的數(shù)字信道化器設(shè)計(jì)與實(shí)現(xiàn)　出處：《西安電子科技大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： 柔性轉(zhuǎn)發(fā)器 數(shù)字信道化技術(shù) 原型濾波器 AGC FPGA

【摘要】：作為寬帶衛(wèi)星移動通信系統(tǒng)中的關(guān)鍵技術(shù)之一,數(shù)字信道化技術(shù)在不改變有效載荷結(jié)構(gòu)的前提下,可以準(zhǔn)確地提取上行鏈路信道中各個(gè)窄帶信號,經(jīng)星上處理后,可重構(gòu)出所需的下行鏈路信號。本文重點(diǎn)研究了星載柔性轉(zhuǎn)發(fā)器的數(shù)字信道化器,該數(shù)字信道化器既可實(shí)現(xiàn)均勻帶寬信號的交換,又可實(shí)現(xiàn)非均勻帶寬信號的交換,且具有簡單高效的實(shí)現(xiàn)結(jié)構(gòu)、良好的靈活性以及較大的容量等特點(diǎn)。本文的主要工作如下:1.給出了一種基于復(fù)指數(shù)調(diào)制濾波器組和多相分解技術(shù)的數(shù)字信道化器高效實(shí)現(xiàn)結(jié)構(gòu),該結(jié)構(gòu)可正確地完成上行鏈路信號的分路、交換和重構(gòu)等星上處理操作,且實(shí)現(xiàn)復(fù)雜度低。2.針對非均勻帶寬數(shù)字信道化器中信號重構(gòu)的特殊需求,提出了一種頻率采樣法和窗函數(shù)法相結(jié)合的原型濾波器設(shè)計(jì)方法,以降低重構(gòu)信號失真度及減少信道間泄漏。仿真結(jié)果表明,該方法能夠使原型濾波器獲得較大的阻帶衰減及較小的通帶拼接抖動。3.搭建了一種非均勻帶寬數(shù)字信道化器的仿真模型。在不同信號調(diào)制(BPSK,QPSK和8PSK)方式下,從子信道間功率泄漏、系統(tǒng)誤比特率和量化性能等方面,對該數(shù)字信道化器的性能進(jìn)行了仿真分析。結(jié)果表明:子信道間的功率泄漏小于-90dB;當(dāng)誤比特率為10-3時(shí),與理想情況相比,該數(shù)字信道化器的性能劣化程度小于0.2dB。4.設(shè)計(jì)了一種數(shù)字AGC電路對信號幅值范圍進(jìn)行壓縮。由于數(shù)字信道化器中電路交換模塊和D/A轉(zhuǎn)換模塊對輸入信號有一定的數(shù)據(jù)位寬要求,因此采用AGC技術(shù)使輸入數(shù)據(jù)穩(wěn)定在一個(gè)確定的動態(tài)范圍內(nèi),從而保證該兩個(gè)模塊的正常工作。仿真結(jié)果表明:該數(shù)字AGC電路的性能滿足系統(tǒng)要求且對非均勻帶寬數(shù)字信道化器的性能影響較小。5.完成了非均勻帶寬數(shù)字信道化器的FPGA設(shè)計(jì)及實(shí)現(xiàn)。首先,給出了一種非均勻帶寬數(shù)字信道化器的FPGA總體設(shè)計(jì)方案;接著,提出了一種新型的濾波器FPGA設(shè)計(jì)方法,用于降低濾波器的硬件實(shí)現(xiàn)復(fù)雜度;最后,對數(shù)字信道化器中各個(gè)子模塊進(jìn)行了FPGA設(shè)計(jì)及實(shí)現(xiàn)。分析結(jié)果表明:該數(shù)字信道化器僅僅需要256個(gè)乘法器,大大降低了硬件資源的消耗。
[Abstract]:As one of the key technologies of broadband satellite mobile communication system, digital channelized technology without changing the payload structure, can accurately extract the narrowband signals in the uplink channel, via satellite processing, can be reconstructed from the downlink signal is required. This paper focuses on the digital channelizers flexible satellite transponder and the digital channel of device can realize the exchange of uniform bandwidth signal, and can realize the non uniform switching bandwidth signal, and has simple structure and high efficiency, good flexibility and large capacity and so on. The main work of this paper are as follows: 1. the efficient structure of a digital channelizer based on complex index modulation filter and polyphase decomposition technique, which can correctly complete the shunt uplink signal, switching and reconstruction of on-board processing operation, and implementation complexity. According to the special needs of non uniform.2. low bandwidth digital signal channel is reconstructed, puts forward the design method of the prototype filter a frequency sampling method and window function method are combined, in order to reduce the signal distortion and reconstruction to reduce the channel leakage. The simulation results show that this method can make the prototype filter to obtain larger stopband the smaller the pass band attenuation and splicing jitter.3. set up a non-uniform bandwidth digital channelizers simulation model. In different signal modulation (BPSK, QPSK and 8PSK) mode, the inter channel leakage power, bit error rate and quantization performance, the performance of the digital channel is conducted simulation analysis. The results show that the inter channel leakage power is less than -90dB; when the bit error rate is 10-3, compared to the ideal case, deterioration of the digital channel of device performance is less than 0.2dB.4. to design a digital AGC The circuit of the signal amplitude range compression. Because the circuit of digital channelizers switching module and D/A conversion module has certain requirements on the data width of the input signal, so using AGC technology to make the input data stability in a certain dynamic range, so as to ensure the normal work of the two modules. The simulation results show that the the performance of AGC digital circuit to meet the requirements of the system and the effect of non-uniform.5. bandwidth digital channelizers completes the design and implementation of FPGA non uniform bandwidth digital channelizer. Firstly, FPGA gives a general design of non-uniform bandwidth digital channelizers; then, we put forward a new the FPGA filter design method is used to reduce the hardware complexity of the filter; finally, the sub module of digital channelizers in the design and implementation of FPGA. The results showed that the number of The channelizer needs only 256 multipliers, which greatly reduces the consumption of hardware resources.

【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN927.23

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本文編號：1411745