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  本文選題：電子設計自動化 + 片上系統(tǒng)(SoC)�。� 參考：《寧波大學》2014年博士論文

【摘要】：隨著集成電路工藝的發(fā)展及便攜設備的廣泛應用,功耗正在成為芯片設計中繼面積和速度以后的重要指標。隨著芯片規(guī)模的增大和功能的復雜化,集成電路設計技術由基于晶體管、邏輯單元設計步入到基于IP核的SoC設計時代,由此產生的新的層次化設計方法給功耗優(yōu)化帶來了新的挑戰(zhàn)。圍繞低功耗SoC設計中的關鍵技術,本文從物理級多電壓SoC布圖規(guī)劃、寄存器傳輸級(Register Transfer Level, RTL)的有限狀態(tài)機狀態(tài)分配和電路級的新型CMOS混合電路分別開展研究,提出了有效的低功耗設計優(yōu)化算法,并采用基準測試電路驗證了算法的性能。論文的研究內容主要包含以下幾個部分: 1.針對多電壓SoC設計中的布圖規(guī)劃,提出了一種有效的算法來進行功耗優(yōu)化和求解速度的加速。通過松弛電壓島的矩形形狀約束,構建非矩形電壓島進一步優(yōu)化功耗。采用非隨機算法完成解空間的搜索加速求解速度,并通過對可能形成一個電壓島的模塊建立超圖并分割,加快電壓島生成速度。實驗結果表明提出的算法在功耗、線長、空白面積和CPU時間上均有優(yōu)勢。 2.針對多電壓SoC設計中P/G供電網絡的電壓降問題,提出了一個基于彈簧模型的電壓降感知電源引腳快速分配算法。通過探究影響電壓降的關鍵參數,在布圖迭代中考慮電源引腳的分配,進一步實現(xiàn)電壓降驅動的電源引腳與布圖規(guī)劃的協(xié)同綜合。不同于傳統(tǒng)的矩陣反轉計算得到P/G網絡的節(jié)點電壓降,采用模塊到電源引腳的加權距離作為優(yōu)化參數引導布圖產生較低的電壓降。然后,采用增量式方法優(yōu)化電壓島的P/G網絡拓撲結構,從而實現(xiàn)P/G網絡的布線面積優(yōu)化。實驗結果表明提出的算法可有效改善P/G網絡性能,優(yōu)化了模塊和電源引腳的放置。 3.針對多電壓SoC布圖規(guī)劃中的電平移位器布局問題,提出了時序約束下的多電壓SoC設計流程。在時序和物理約束下同時考慮電壓分配、電平移位器布局、電壓島生成等步驟。提出了在網表級插入虛擬電平移位器的方法來保留較多的空白面積,以便于電平移位器布局。與之前的工作不考慮物理信息對電壓分配的影響不同,為使時序和物理約束同時得到滿足,考慮了物理信息的反饋,通過建立內循環(huán)使得電壓分配和電平移位器布局交互進行滿足直到所有的約束。 4.針對IP核模塊中的時序電路,提出了基于拉格朗日松弛技術的峰值電流與開關活動性協(xié)同優(yōu)化算法。通過遺傳算法進行解空間的搜索,并在每次迭代中采用次梯度優(yōu)化算法進行拉格朗日乘子的更新。采用啟發(fā)式算法確定峰值電流的上界,并返回最優(yōu)解。通過對IWLS’93和ITC’99的測試電路結果比較,提出的算法較先前的算法可優(yōu)化峰值電流分別達到45.27%和25.13%；優(yōu)化開關活動性達6.31%。與確定性方法相比,提出的算法可在較短的CPU時間內得到相同峰值電流。 5.針對新型CMOS混合電路,研究了SoC實現(xiàn)的關鍵步驟,單元映射算法。通過將映射問題進行拉格朗日松弛,采用包含二維塊交叉算子、變異算子和自學習算子的進化算法作為解空間的搜索引擎完成求解。實驗結果顯示其可增大電路的求解規(guī)模,且在面積、時延和CPU時間上均有較大優(yōu)勢；針對高扇出邏輯門難于映射,提出了基于邏輯復制和反相器對插入法進行高扇出的分割完成邏輯變換,實驗結果顯示變換后的電路進一步改進了性能,降低了映射的復雜度。
[Abstract]:With the development of integrated circuit technology and the wide application of portable equipment , the power consumption is becoming an important index after chip design relay area and speed . With the increase of chip scale and complexity of function , the new hierarchical design method has brought new challenges to power consumption optimization .

1 . Aiming at the layout planning in multi - voltage SoC design , an effective algorithm is put forward to accelerate the power consumption optimization and the solution speed . The non - rectangular voltage island is further optimized by the rectangular shape constraint of the relaxation voltage island . The non - random algorithm is used to complete the search acceleration solution speed of the space . The experimental results show that the proposed algorithm has the advantages of power consumption , line length , blank area and CPU time .

2 . Aiming at the voltage drop problem of P / G power supply network in multi - voltage SoC design , a fast distribution algorithm of voltage drop sensing power supply pin based on spring model is put forward .

3 . In order to solve the problem of level shifter layout in multi - voltage SoC layout planning , a multi - voltage SoC design flow under timing constraints is put forward . At the same time , the steps of voltage distribution , level shifter layout and voltage island generation are considered under the timing and physical constraints .

4 . Aiming at the sequential circuit in IP core module , the optimal algorithm for peak current and switching activity based on Lagrangian relaxation technique is proposed . The algorithm is used to search the solution space . The upper bound of peak current is determined by means of heuristic algorithm , and the optimal solution is returned . The proposed algorithm can optimize the peak current by 45.27 % and 25.13 % by comparing the results of the test circuits of IWLS ' 93 and ITC ' 99 .
The optimized switching activity is 6.31 % . Compared with the deterministic method , the proposed algorithm can obtain the same peak current in the shorter CPU time .

5 . Aiming at the new CMOS hybrid circuits , the key steps and the unit mapping algorithm of SoC implementation are studied . The mapping problem is Lagrangian relaxation , and the evolutionary algorithm including two - dimensional block crossover operator , mutation operator and self - learning operator is used as the search engine to solve the problem . The experimental results show that it can increase the solution size of the circuit and has great advantage in area , time delay and CPU time .
According to the difficult mapping of high - fan - out logic gates , a logic - based replication and inverter - pair insertion method is proposed to perform the high - fan - out logic transformation . The experimental results show that the transformed circuit further improves the performance and reduces the complexity of the mapping .
【學位授予單位】：寧波大學
【學位級別】：博士
【學位授予年份】：2014
【分類號】：TP391.41

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本文編號：2087870