發(fā)布時(shí)間：2018-07-01 12:59

  本文選題：電子設(shè)計(jì)自動(dòng)化 + 片上系統(tǒng)(SoC)��； 參考：《寧波大學(xué)》2014年博士論文

【摘要】：隨著集成電路工藝的發(fā)展及便攜設(shè)備的廣泛應(yīng)用,功耗正在成為芯片設(shè)計(jì)中繼面積和速度以后的重要指標(biāo)。隨著芯片規(guī)模的增大和功能的復(fù)雜化,集成電路設(shè)計(jì)技術(shù)由基于晶體管、邏輯單元設(shè)計(jì)步入到基于IP核的SoC設(shè)計(jì)時(shí)代,由此產(chǎn)生的新的層次化設(shè)計(jì)方法給功耗優(yōu)化帶來了新的挑戰(zhàn)。圍繞低功耗SoC設(shè)計(jì)中的關(guān)鍵技術(shù),本文從物理級(jí)多電壓SoC布圖規(guī)劃、寄存器傳輸級(jí)(Register Transfer Level, RTL)的有限狀態(tài)機(jī)狀態(tài)分配和電路級(jí)的新型CMOS混合電路分別開展研究,提出了有效的低功耗設(shè)計(jì)優(yōu)化算法,并采用基準(zhǔn)測(cè)試電路驗(yàn)證了算法的性能。論文的研究?jī)?nèi)容主要包含以下幾個(gè)部分: 1.針對(duì)多電壓SoC設(shè)計(jì)中的布圖規(guī)劃,提出了一種有效的算法來進(jìn)行功耗優(yōu)化和求解速度的加速。通過松弛電壓島的矩形形狀約束,構(gòu)建非矩形電壓島進(jìn)一步優(yōu)化功耗。采用非隨機(jī)算法完成解空間的搜索加速求解速度,并通過對(duì)可能形成一個(gè)電壓島的模塊建立超圖并分割,加快電壓島生成速度。實(shí)驗(yàn)結(jié)果表明提出的算法在功耗、線長(zhǎng)、空白面積和CPU時(shí)間上均有優(yōu)勢(shì)。 2.針對(duì)多電壓SoC設(shè)計(jì)中P/G供電網(wǎng)絡(luò)的電壓降問題,提出了一個(gè)基于彈簧模型的電壓降感知電源引腳快速分配算法。通過探究影響電壓降的關(guān)鍵參數(shù),在布圖迭代中考慮電源引腳的分配,進(jìn)一步實(shí)現(xiàn)電壓降驅(qū)動(dòng)的電源引腳與布圖規(guī)劃的協(xié)同綜合。不同于傳統(tǒng)的矩陣反轉(zhuǎn)計(jì)算得到P/G網(wǎng)絡(luò)的節(jié)點(diǎn)電壓降,采用模塊到電源引腳的加權(quán)距離作為優(yōu)化參數(shù)引導(dǎo)布圖產(chǎn)生較低的電壓降。然后,采用增量式方法優(yōu)化電壓島的P/G網(wǎng)絡(luò)拓?fù)浣Y(jié)構(gòu),從而實(shí)現(xiàn)P/G網(wǎng)絡(luò)的布線面積優(yōu)化。實(shí)驗(yàn)結(jié)果表明提出的算法可有效改善P/G網(wǎng)絡(luò)性能,優(yōu)化了模塊和電源引腳的放置。 3.針對(duì)多電壓SoC布圖規(guī)劃中的電平移位器布局問題,提出了時(shí)序約束下的多電壓SoC設(shè)計(jì)流程。在時(shí)序和物理約束下同時(shí)考慮電壓分配、電平移位器布局、電壓島生成等步驟。提出了在網(wǎng)表級(jí)插入虛擬電平移位器的方法來保留較多的空白面積,以便于電平移位器布局。與之前的工作不考慮物理信息對(duì)電壓分配的影響不同,為使時(shí)序和物理約束同時(shí)得到滿足,考慮了物理信息的反饋,通過建立內(nèi)循環(huán)使得電壓分配和電平移位器布局交互進(jìn)行滿足直到所有的約束。 4.針對(duì)IP核模塊中的時(shí)序電路,提出了基于拉格朗日松弛技術(shù)的峰值電流與開關(guān)活動(dòng)性協(xié)同優(yōu)化算法。通過遺傳算法進(jìn)行解空間的搜索,并在每次迭代中采用次梯度優(yōu)化算法進(jìn)行拉格朗日乘子的更新。采用啟發(fā)式算法確定峰值電流的上界,并返回最優(yōu)解。通過對(duì)IWLS’93和ITC’99的測(cè)試電路結(jié)果比較,提出的算法較先前的算法可優(yōu)化峰值電流分別達(dá)到45.27%和25.13%；優(yōu)化開關(guān)活動(dòng)性達(dá)6.31%。與確定性方法相比,提出的算法可在較短的CPU時(shí)間內(nèi)得到相同峰值電流。 5.針對(duì)新型CMOS混合電路,研究了SoC實(shí)現(xiàn)的關(guān)鍵步驟,單元映射算法。通過將映射問題進(jìn)行拉格朗日松弛,采用包含二維塊交叉算子、變異算子和自學(xué)習(xí)算子的進(jìn)化算法作為解空間的搜索引擎完成求解。實(shí)驗(yàn)結(jié)果顯示其可增大電路的求解規(guī)模,且在面積、時(shí)延和CPU時(shí)間上均有較大優(yōu)勢(shì)；針對(duì)高扇出邏輯門難于映射,提出了基于邏輯復(fù)制和反相器對(duì)插入法進(jìn)行高扇出的分割完成邏輯變換,實(shí)驗(yàn)結(jié)果顯示變換后的電路進(jìn)一步改進(jìn)了性能,降低了映射的復(fù)雜度。
[Abstract]:With the development of integrated circuit technology and the wide application of portable equipment , the power consumption is becoming an important index after chip design relay area and speed . With the increase of chip scale and complexity of function , the new hierarchical design method has brought new challenges to power consumption optimization .

1 . Aiming at the layout planning in multi - voltage SoC design , an effective algorithm is put forward to accelerate the power consumption optimization and the solution speed . The non - rectangular voltage island is further optimized by the rectangular shape constraint of the relaxation voltage island . The non - random algorithm is used to complete the search acceleration solution speed of the space . The experimental results show that the proposed algorithm has the advantages of power consumption , line length , blank area and CPU time .

2 . Aiming at the voltage drop problem of P / G power supply network in multi - voltage SoC design , a fast distribution algorithm of voltage drop sensing power supply pin based on spring model is put forward .

3 . In order to solve the problem of level shifter layout in multi - voltage SoC layout planning , a multi - voltage SoC design flow under timing constraints is put forward . At the same time , the steps of voltage distribution , level shifter layout and voltage island generation are considered under the timing and physical constraints .

4 . Aiming at the sequential circuit in IP core module , the optimal algorithm for peak current and switching activity based on Lagrangian relaxation technique is proposed . The algorithm is used to search the solution space . The upper bound of peak current is determined by means of heuristic algorithm , and the optimal solution is returned . The proposed algorithm can optimize the peak current by 45.27 % and 25.13 % by comparing the results of the test circuits of IWLS ' 93 and ITC ' 99 .
The optimized switching activity is 6.31 % . Compared with the deterministic method , the proposed algorithm can obtain the same peak current in the shorter CPU time .

5 . Aiming at the new CMOS hybrid circuits , the key steps and the unit mapping algorithm of SoC implementation are studied . The mapping problem is Lagrangian relaxation , and the evolutionary algorithm including two - dimensional block crossover operator , mutation operator and self - learning operator is used as the search engine to solve the problem . The experimental results show that it can increase the solution size of the circuit and has great advantage in area , time delay and CPU time .
According to the difficult mapping of high - fan - out logic gates , a logic - based replication and inverter - pair insertion method is proposed to perform the high - fan - out logic transformation . The experimental results show that the transformed circuit further improves the performance and reduces the complexity of the mapping .
【學(xué)位授予單位】：寧波大學(xué)
【學(xué)位級(jí)別】：博士
【學(xué)位授予年份】：2014
【分類號(hào)】：TP391.41

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本文編號(hào)：2087870