本文關(guān)鍵詞： 現(xiàn)場影像增強 FPGA硬件加速 高動態(tài)范圍視頻 運動影像放大 高速串行總線接口　出處：《中國科學(xué)技術(shù)大學(xué)》2017年博士論文　論文類型：學(xué)位論文

【摘要】：隨著處理器性能的不斷提升,圖像、影像中越來越多的信息被直觀化地呈現(xiàn)給用戶。然而,面對用戶在直觀化成像上越來越高的應(yīng)用需求,信息的數(shù)據(jù)量龐大且需要實時處理�；趫D像處理平臺進(jìn)行性能改進(jìn)的方法往往難以達(dá)到直觀化成像要求,實時性和系統(tǒng)帶寬難以保證。圖像處理平臺多采用單攝像頭單傳感器模塊對圖像進(jìn)行采集,且平臺多采用同構(gòu)處理器架構(gòu),配合主機完成后處理任務(wù),其架構(gòu)更多依賴于軟件算法來完成用戶應(yīng)用需求的響應(yīng),主機運行的軟件算法處理速度較慢,達(dá)不到直觀化成像的實時性要求,比如立體視覺、虛擬現(xiàn)實、現(xiàn)實增強等應(yīng)用就難以用圖像處理平臺來滿足實時性需求。此外,高分辨率、高幀率的場景影像采集需要較高的前端總線帶寬來完成影像數(shù)據(jù)的傳輸任務(wù),基于圖像處理平臺的改進(jìn)并不能達(dá)到影像處理的帶寬需求。因此,圖像處理平臺的后處理思路無法滿足直觀化成像所帶來的實時性、帶寬需求,針對用戶直觀化應(yīng)用要求,本文提出現(xiàn)場影像增強方法,該方法主要完成圖像增強領(lǐng)域中直觀化成像的實時性和帶寬需求,對影像信息進(jìn)行還原和增強處理,得到實時的現(xiàn)場影像增強處理結(jié)果。利用FPGA進(jìn)行算法優(yōu)化和硬件加速,可以解決直觀化應(yīng)用中的實時性瓶頸;利用定制化的現(xiàn)場高速總線接口 UPI(PCIe/SRIO復(fù)用接口)可以解決直觀化應(yīng)用中的帶寬瓶頸。現(xiàn)場影像增強方法分為兩個部分:首先,需要對影像現(xiàn)場信息進(jìn)行還原,以保證信息獲取范圍的準(zhǔn)確性。本文采用了高動態(tài)范圍成像算法對場景信息進(jìn)行還原處理,并對單相機成像、多相機成像和單鏡頭多傳感器成像等方法進(jìn)行了歸納總結(jié),提出了一種能夠?qū)崟r處理的高動態(tài)范圍視頻算法。其次,需要對場景信息進(jìn)行增強處理,本文梳理了幾種影像增強方法及各自優(yōu)缺點,精簡了歐拉影像放大方法中的拉普拉斯金字塔構(gòu)建方法,實現(xiàn)了 ⅡR濾波的流水線處理,提出了一種快速硬件實現(xiàn)的歐拉影像放大算法。本文針對現(xiàn)場影像增強方法的幾個關(guān)鍵問題進(jìn)行了研究,并給出了系統(tǒng)性的硬件加速方案。主要的研究工作和創(chuàng)新點:(1)歸納總結(jié)了當(dāng)前高動態(tài)范圍圖像算法和視頻算法的研究成果,提出了實時的高動態(tài)范圍視頻算法及硬件加速方法。首先,針對高動態(tài)范圍成像算法,本文提出了一種改進(jìn)的Ward權(quán)值函數(shù)選取方法,并利用三階貝塞爾函數(shù)推導(dǎo)了相機響應(yīng)曲線的擬合公式,可以在不需要精確知道曝光時間的情況下還原照度圖:同時,本文提出了一種優(yōu)化的全局色調(diào)映射算子,在不影響對比度的情況下降低了高亮區(qū)域的照度值,保證圖像中不會出現(xiàn)飽和失真;此外,本文對高動態(tài)范圍視頻中的頻閃問題提出了硬件解決方法,采用漏積分器模型對獨立計算的每幀亮度參數(shù)進(jìn)行處理,使得色調(diào)映射過程中各幀亮度參數(shù)相對統(tǒng)一。針對算法硬件加速過程遇到的存儲密集問題,本文對相機響應(yīng)曲線進(jìn)行四叉樹壓縮編碼,相比于直接存儲相機響應(yīng)曲線的方法,本文方法可以節(jié)省至少99.6%的BRAM資源;針對算法硬件加速過程遇到的計算密集問題,本文采用多項式逼近方法將復(fù)雜的指數(shù)和對數(shù)運算簡化為移位和加法運算,同時利用乒乓緩沖區(qū)進(jìn)行多路并行流水,結(jié)合FPGA內(nèi)嵌的DSP slice資源,加快軟件算法循環(huán)語句運算速度。相比于Lapray和Mann等人提出的FPGA硬件處理平臺,本文處理相同分辨率的影像所需要的時間較短,在120MHz的系統(tǒng)時鐘下,針對分辨率為1920×1080的19.58MB標(biāo)準(zhǔn)視頻數(shù)據(jù),可在15.3ms內(nèi)完成一幀視頻圖像的輸出。(2)梳理了當(dāng)前運動放大算法的研究成果,對拉格朗日影像放大方法和歐拉影像放大方法的優(yōu)缺點進(jìn)行了分析,論證了拉格朗日放大方法不適合硬件實現(xiàn)的原因。提出了一種快速硬件實現(xiàn)的歐拉影像放大算法,該方法通過削減金字塔數(shù)量、固定放大因子,在不影響直觀化顯示效果的情況下,相比于利用Matlab軟件在Intel(R)Xeon(R)處理器(3.3GHz)實現(xiàn)的軟件算法,能夠獲得16.1倍的硬件加速比。(3)對前端總線的定制化方法和實時圖像處理平臺構(gòu)建方法進(jìn)行了總結(jié)和歸納,提出了以多個消息隊列和影像增強引擎為核心的硬件加速方法。采用兩片F(xiàn)PGA完成現(xiàn)場影像增強任務(wù),基于功能級的任務(wù)切割方法對FPGA多任務(wù)進(jìn)行調(diào)度,前端總線采用PCIe總線,FPGA芯片間互聯(lián)通過SRIO總線完成。本文設(shè)計了一種靈活的FPGA高速串行總線接口UPI(Unified PHY Interface),并給出相應(yīng)的API函數(shù)。該接口采用共PHY的物理層架構(gòu),利用同一高速串行收發(fā)器時分傳輸PCle協(xié)議包和SRIO協(xié)議包,完成前端幀數(shù)據(jù)的采集任務(wù),提高了處理平臺的靈活性和帶寬需求。
[Abstract]:As processor performance continues to improve, more and more image, the image information is intuitively presented to the user. However, facing the needs of users in a more intuitive to the information of the huge amount of data and require real-time processing. The image processing method based on the improved platform in the performance is often difficult to achieve visualization the requirements of imaging, real-time and bandwidth of the system. It is difficult to guarantee the image processing platform using single camera single sensor module to collect the image, and the platform of multi homogeneous processor architecture, with the host to complete the postprocessing task, its architecture is more dependent on the software algorithm to complete the response to user application requirements, software algorithms running slower host that is not up to the requirements of real-time visual imaging, such as stereo vision, virtual reality, augmented reality applications will be difficult to use image processing platform To meet the real-time demand. In addition, high resolution, scene image acquisition need high bandwidth front bus to complete the image data transmission task with high frame rate and bandwidth requirements of improved image processing platform and can not achieve the image processing based on image processing platform. Therefore, the postprocessing ideas cannot satisfy the intuitive real-time imaging brought the bandwidth requirements for the user intuitive application requirements, this scene image enhancement method, this method is mainly to complete the image enhancement of real-time and bandwidth requirements of the field of view of imaging, the image information reduction and enhancement processing, real-time field image enhancement processing results. The optimal algorithm and hardware accelerated by FPGA. Can solve the bottleneck of real-time visualization applications; using customized on-site high-speed UPI bus interface (PCIe/SRIO interface) can be solved directly The bandwidth bottleneck of the application of the scene. The image enhancement method is divided into two parts: first, the need for image information of the scene to restore, to ensure the accuracy of range information is obtained. This paper adopts the algorithm of high dynamic range imaging for reducing on the scene information, and the single phase imaging machine, multi camera imaging and single lens multi sensor the imaging methods are summarized, and put forward a kind of high dynamic range video algorithm capable of real-time processing. Secondly, the need for information of the scene is enhanced, this paper reviews several image enhancement methods and their advantages and disadvantages, construction method of Laplasse Pyramid to streamline the Euler image magnification method, realizes the pipelined R filter II the proposed image Euler implementation of a fast hardware algorithm. Aiming at the scene image magnification is studied several key problems of enhancement, And gives the system hardware acceleration scheme. The main research works and innovations: (1) summarizes the current research results of high dynamic range image algorithm and video algorithm, proposed high dynamic range video real-time algorithm and hardware acceleration method. First, according to the high dynamic range imaging algorithm is proposed in this paper. A selection method of Ward weight function improved, and using the three order Bessel function deduced camera response curve fitting formula, can accurately know the exposure time under the condition of illumination reduction in need. At the same time, this paper proposes an optimized global tone mapping operator, without affecting the contrast is reduced under the condition the highlighted area illumination, ensure that the image will not appear in the saturation distortion; in addition, this paper proposes a hardware solution for the flicker problem of high dynamic range video, using the integral model of leakage Each frame brightness parameter independent calculation processing, make the parameters of tone mapping process each frame brightness is relatively uniform. The algorithm hardware accelerated storage intensive problems met in the process, the four fork tree on camera response curve compression encoding, compared to the direct storage ring camera method should curve, this method can save at least 99.6% BRAM resources; for hardware accelerated algorithm for computing intensive problems met in the process, this paper uses the polynomial approximation method of the complex exponential and logarithm arithmetic is simplified to shift and addition operations, and the use of ping-pong buffer for multi-channel parallel pipeline, combined with embedded FPGA DSP slice resources, speed up the software algorithm loop speed. Compared to the FPGA hardware platform Lapray and Mann proposed the same resolution, the image processing required for a short time, the system clock of 120MHz, According to the 19.58MB standard video data resolution is 1920 * 1080, can complete the output of a frame of video images in 15.3ms. (2) reviews the results of research on the motion amplification algorithm, the advantages and disadvantages of image amplification method and Euler Lagrange image amplification method is analyzed, the reason that Lagrange amplification method is not suitable for hardware implementation the proposed hardware implementation of a fast Euler image magnification algorithm, this method by reducing the number of Pyramid, fixed amplification factor, without affecting the visual display effect, compared to the use of Matlab software in Intel (R) Xeon (R) processor (3.3GHz) software algorithm, can get 16.1 times the hardware acceleration ratio. (3) method of customized front bus and real-time and summarized image processing platform construction method, put forward to a plurality of message queue and image enhancement engine The core of the hardware accelerated method. Using two pieces of FPGA to complete the task of image enhancement, the task of cutting function level scheduling method based on multi task FPGA, the front bus is PCIe bus FPGA chip interconnection via SRIO bus. This paper describes the design of a flexible FPGA high speed serial bus interface UPI (Unified PHY Interface) API function, is proposed. The interface of the physical layer structure of PHY, using the same high-speed serial transceiver for time division transmission PCle protocol and SRIO protocol packets, complete front-end frame data acquisition task, improves the flexibility and bandwidth requirements of processing platform.

【學(xué)位授予單位】：中國科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：博士
【學(xué)位授予年份】：2017
【分類號】：TP391.41

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本文編號：1457494