本文關(guān)鍵詞： 離散傅里葉變換 浮點(diǎn) 定點(diǎn) 互質(zhì)數(shù)乘積 FPGA ASIC 自動(dòng)生成 綜合 卷積神經(jīng)網(wǎng)絡(luò)　出處：《中國(guó)科學(xué)技術(shù)大學(xué)》2017年碩士論文　論文類型：學(xué)位論文

【摘要】：離散傅里葉變換(DFT)被廣泛應(yīng)用于幾乎所有的科學(xué)與工程計(jì)算領(lǐng)域中,特別是在一些現(xiàn)代大規(guī)模數(shù)據(jù)處理應(yīng)用中,比如音視頻信號(hào)數(shù)據(jù)處理,使用到了越來(lái)越多計(jì)算復(fù)雜且硬件需求高的特性,例如超長(zhǎng)點(diǎn)數(shù)和非二的正整數(shù)次冪點(diǎn)的硬件離散傅里葉變換單元和擁有寬計(jì)算范圍以及高有效精度的浮點(diǎn)運(yùn)算。現(xiàn)代離散傅里葉變換應(yīng)用諸如音視頻編解碼、正交分頻復(fù)用、大數(shù)據(jù)處理等,其對(duì)運(yùn)算實(shí)時(shí)性要求高需要硬件運(yùn)算單元,對(duì)精度和通用性要求高需要滿足IEEE-754標(biāo)準(zhǔn)規(guī)范的浮點(diǎn)數(shù),對(duì)采樣點(diǎn)數(shù)要求高需要長(zhǎng)點(diǎn)數(shù)以及非二的正整數(shù)次冪點(diǎn)數(shù)的離散傅里葉變換。本文提出了一種基于矩陣分解的用于互質(zhì)數(shù)乘積長(zhǎng)度的非二的正整數(shù)次冪點(diǎn)數(shù)的傅里葉變換算法,并設(shè)計(jì)了可實(shí)現(xiàn)該算法的離散傅里葉變換硬件架構(gòu)綜合工具—AutoNFT。主要工作內(nèi)容如下:本文研究了基于矩陣分解的可用于兩兩互質(zhì)數(shù)乘積點(diǎn)數(shù)的離散傅里葉變換算法。該算法與已有的用于小奇數(shù)(3、5、9)乘二的正整數(shù)次冪點(diǎn)數(shù)的算法相比,具有更廣的應(yīng)用點(diǎn)數(shù)的范圍;通過(guò)嚴(yán)謹(jǐn)?shù)臄?shù)學(xué)推導(dǎo)證明了算法的正確性,并給出了相較于傳統(tǒng)算法不同的輸入輸出順序計(jì)算公式,以實(shí)現(xiàn)互質(zhì)數(shù)離散傅立葉變換模塊間的級(jí)聯(lián)。本文設(shè)計(jì)的AutoNFT綜合工具可以自動(dòng)生成全流水線架構(gòu)的硬件離散傅里葉變換單元,支持二的正整數(shù)次冪點(diǎn)數(shù)和兩兩互質(zhì)數(shù)乘積點(diǎn)數(shù),并具有高度的可移植性,同時(shí)支持定點(diǎn)、浮點(diǎn)采樣。提出了用于全流水線結(jié)構(gòu)及自動(dòng)級(jí)聯(lián)的自動(dòng)生成算法,能夠通過(guò)基于移位寄存器的先入先出單元有效處理相比基2/4算法更高效的分裂基算法的L型結(jié)構(gòu);設(shè)計(jì)了包含八級(jí)流水線的高性能浮點(diǎn)加法與乘法單元,可在SMIC 40納米工藝下工作在1Ghz頻率。本文在Zynq 7000平臺(tái)下對(duì)定點(diǎn)及浮點(diǎn)運(yùn)算單元、手寫(xiě)數(shù)字神經(jīng)網(wǎng)絡(luò)、16點(diǎn)和15點(diǎn)浮點(diǎn)離散傅里葉變換單元進(jìn)行了驗(yàn)證。給出了手寫(xiě)數(shù)字識(shí)別網(wǎng)絡(luò)LeNet-5的FPGA實(shí)現(xiàn),相比通用計(jì)算器件如CPU、GPU實(shí)現(xiàn),在達(dá)到軟件算法相同的低錯(cuò)誤率0.999%的同時(shí),其消耗運(yùn)算時(shí)間比Caffe快37%,并且能耗低達(dá)93.7%。同時(shí),本文也在SMIC40納米工藝和500Mhz頻率下,完成了對(duì)長(zhǎng)點(diǎn)數(shù)以及質(zhì)數(shù)乘積點(diǎn)數(shù)的定點(diǎn)以及浮點(diǎn)離散傅里葉變換單元的綜合和仿真。特別地對(duì)于256點(diǎn)離散傅里葉變換單元,其每秒可處理1150億個(gè)定點(diǎn)采樣;對(duì)于30點(diǎn)離散傅里葉變換單元,其每秒可處理135億個(gè)浮點(diǎn)采樣。
[Abstract]:Discrete Fourier transform (DFT) is widely used in almost all fields of scientific and engineering computing, especially in some modern large-scale data processing applications, such as audio and video signal data processing. More and more complex computing and high hardware requirements are used. For example, the hardware discrete Fourier transform unit of super-long points and non-binary positive integer power points and floating-point operations with wide calculation range and high efficient precision.; Modern discrete Fourier transform applications such as audio and video coding and decoding. Orthogonal frequency division multiplexing, big data processing, etc., which requires high real-time operation requirements of hardware operation unit, high accuracy and versatility requirements to meet the IEEE-754 standard standard floating-point number. The discrete Fourier transform which requires long points and non-binary positive integer power points is required for high sampling points. In this paper, a new Fourier transform based on matrix decomposition is proposed for the length of the product length of mutual prime numbers. Riefer transform algorithm. A hardware synthesis tool for discrete Fourier transform (DFT)-AutoNFT is designed. The main work is as follows:. In this paper, we study the discrete Fourier transform (DFT) algorithm based on matrix decomposition, which can be used for the product points of pairwise prime numbers. 3. Compared with the algorithm of multiplying the number of positive integers by two, the algorithm has a wider range of points of application. The correctness of the algorithm is proved by rigorous mathematical derivation, and the formulas for calculating the order of input and output in comparison with the traditional algorithm are given. In order to realize the concatenation between the discrete Fourier transform modules, the AutoNFT synthesis tool designed in this paper can automatically generate the hardware discrete Fourier transform unit of the full pipeline architecture. Two positive integer power points and pairwise prime number product points are supported with high portability and fixed-point and floating-point sampling. An automatic generating algorithm for full pipeline structure and automatic cascade is proposed. The L-type structure of the split base algorithm, which is more efficient than the base 2/4 algorithm, can be effectively processed by the first-in-first-out unit based on the shift register. A high performance floating-point addition and multiplication unit including 8-stage pipeline is designed. It can work at 1 Ghz frequency in SMIC 40 nanoscale process. In this paper, fixed point and floating-point operation unit and handwritten digital neural network are studied on Zynq 7000 platform. 16:00 and 15:00 floating-point discrete Fourier transform units are verified. The FPGA implementation of handwritten numeral recognition network LeNet-5 is given, compared with that of general calculators such as CPU / GPU. At the same time, the software algorithm has the same low error rate (0.999%), which consumes 37 times faster than Caffe, and has a low energy consumption of 93.70.At the same time. In this paper, SMIC40 nanotechnology and 500MHz frequency are also used. The synthesis and simulation of fixed-point and floating-point discrete Fourier transform units for long points and prime product points are completed, especially for 256 points discrete Fourier transform units. It can handle 115 billion fixed-point samples per second; For a 30-point discrete Fourier transform unit, it can handle 13. 5 billion floating-point samples per second.
【學(xué)位授予單位】：中國(guó)科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TP301.6

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