嵌入式系統(tǒng)已經(jīng)成為人們?nèi)粘Ｉ钪胁豢苫蛉钡囊徊糠�。智能手機(jī),高清電視,洗衣機(jī)和汽車牽引力控制系統(tǒng)不僅使生活更舒適,而且使生活更安全。低成本,高性能和高能效的需求已經(jīng)成為系統(tǒng)設(shè)計的關(guān)鍵,為了實現(xiàn)這些需求,以加速器為中心的異構(gòu)計算成為有效利用硬件的最佳方式。本論文研究了高性能和高能效嵌入式系統(tǒng)的兩種設(shè)計方法。第一種方法是基于應(yīng)用剖析來定制處理器架構(gòu)。第二種方法是設(shè)計專用加速器,將其集成到處理器的數(shù)據(jù)路徑,以增強(qiáng)性能。第一種方法涉及到FlexCore處理器中的指令解壓縮器的實現(xiàn)以及壓縮和解壓縮方案的分析。指令解壓縮器由VHDL設(shè)計和實現(xiàn),并使用Cadence RTL編譯器進(jìn)行了綜合。針對指令解壓縮器的硬件實現(xiàn),本文分析了壓縮方案中不同參數(shù)的影響。由于節(jié)省了內(nèi)存占用,指令解壓縮器大大提高了 FlexCore的性能。然后,本文利用兩種類型的加法器電路,紋波進(jìn)位加法器(RCA)和Sklansky型加法器(SKL),實現(xiàn)了基本算術(shù)邏輯單元(ALU)。本文在專用集成電路(ASIC)平臺上,使用了 VHDL和標(biāo)準(zhǔn)元件設(shè)計了 ALU。綜合結(jié)果表明,ALU-RCA的面積變化比ALU-SKL更快,因為ALU-...

【文章頁數(shù)】：174 頁

【學(xué)位級別】：博士

【文章目錄】：
摘要
Abstract
Chapter 1 Introduction
    1.1 Background and Related Work
    1.2 Problem Statement
    1.3 Thesis Outline
Chapter 2 Optimization of Core Processor Architecture
    2.1 Instruction Decompressor Design
        2.1.1 FlexCore Processor Architecture
        2.1.2 Flexible Datapath Interconnect
        2.1.3 The FlexSoC Framework
        2.1.4 Existing Compression Schemes
        2.1.5 Implementation of Compression scheme
        2.1.6 Instruction Decompressor
        2.1.7 Implementation of Instruction Decompressor
        2.1.8 Discussion on Synthesis Results
    2.2 Arithmetic Logic Unit Design
        2.2.1 ALU Design- Verification
        2.2.2 ALU Design- Basic Synthesis
        2.2.3 ALU Design- Design Respin and Power analysis
        2.2.4 ALU Design- Place and Route
    2.3 Conclusion
Chapter 3 Application Specific Accelerator Design
    3.1 CORDIC Accelerator Design
        3.1.1 Standard CORDIC Algorithm
        3.1.2 Hardware Mapping of Standard CORDIC
        3.1.3 Standard CORDIC Hardware Accelerator
        3.1.4 Modified CORDIC Algorithm
        3.1.5 Modified CORDIC Hardware Accelerator
    3.2 CRC Accelerator Design
        3.2.1 CRC Computation Techniques
        3.2.2 CRC Accelerator Implementation
        3.2.3 Integration of CRC Accelerator with MicroBlaze
    3.3 Viterbi Accelerator Design
        3.3.1 Convolutional Encoding and Viterbi Decoding
        3.3.2 Initial Viterbi Decoder
        3.3.3 Mixed HW/SW Viterbi Accelerator
        3.3.4 Integration of Viterbi Accelerator with MicroBlaze
    3.4 Conclusion
Chapter 4 Heterogeneous Architectures
    4.1 Digital Hearing Aid
        4.1.1 Types of Hearing Aids
        4.1.2 Signal Processing Techniques
        4.1.3 Basic Description of System
        4.1.4 Mixed Hardware/Software Implementation
        4.1.5 Hardware Implementation
    4.2 Distance and Speed Measurement
        4.2.1 Software Implementation
        4.2.2 Mixed Hardware/Software Implementation
        4.2.3 Hardware Implementation
        4.2.4 ASIC Implementation
    4.3 Conclusion
Chapter 5 Conclusion and Future Directions
    5.1 Summary
    5.2 Future Directions
References
Acknowledgements
List of Publications



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