【摘要】：靜態(tài)隨機存儲器(SRAM)作為最重要的存儲器之一,是現(xiàn)代SoC中關鍵部分,其功耗及穩(wěn)定性等各方面性能是整個芯片性能的關鍵因素。半導體工藝進入納米級以后,參數(shù)波動越來越大,漏電流功耗也越來越大,使得SRAM的設計在穩(wěn)定性、功耗等方面面臨新的問題。 論文通過分析納米級工藝下集成電路設計面臨功耗及穩(wěn)定性方面的問題,進而對SRAM單元的功耗、穩(wěn)定性等方面進行了深入的研究與分析。介紹SRAM單元電路中降低功耗的門控電源機制、晶體管堆疊機制、體偏置效應及使用FinFET晶體管方法的應用并比較其結果,并介紹分析SRAM結構穩(wěn)定性的指標靜態(tài)噪聲容限,增強單元電路穩(wěn)定性的動態(tài)電源機制以及幾種提高穩(wěn)定性的SRAM單元結構。論文分析了SRAM中動態(tài)功耗與靜態(tài)功耗的來源并通過仿真分析其大小,同時還分析了結構中噪聲的來源,介紹了蒙特卡羅分析法,并通過2000次蒙特卡羅仿真分析了噪聲對SRAM結構讀靜態(tài)噪聲容限的影響。 論文通過對SRAM單元功耗、噪聲來源及改進思路的研究,進行了結構上的重新設計,并在此基礎上提出了一種新型的單端讀不對稱8晶體管SRAM單元結構。繼而詳細介紹了該新結構的組成及工作原理,分析其功耗及噪聲來源。最后對比標準6晶體管SRAM單元各方面的性能,對新8晶體管單元的功耗及穩(wěn)定性進行評估。 本文在提出的新結構基礎上通過輔以門控電源技術、亞閾值電壓機制、動態(tài)電源法以及使用雙柵結構晶體管來進一步提高其功耗、穩(wěn)定性方面的性能,并比較結果。
[Abstract]:As one of the most important memory, static random access memory (SRAM) is a key part of modern SoC. Its power consumption and stability are the key factors of the whole chip performance. After the semiconductor process enters the nanometer level, the parameters fluctuate more and more, and the leakage current power consumption is also more and more large, which makes the design of SRAM face new problems in stability, power consumption and so on. In this paper, the power consumption and stability of integrated circuit design in nanometer process are analyzed, and then the power consumption and stability of SRAM unit are deeply studied and analyzed. This paper introduces the gated power supply mechanism, transistor stacking mechanism, volume bias effect and the application of FinFET transistor method in SRAM cell circuits, and compares the results, and introduces the static noise tolerance of SRAM structure stability, the dynamic power supply mechanism to enhance the stability of cell circuits and several SRAM cell structures to improve the stability. In this paper, the sources of dynamic power consumption and static power consumption in SRAM are analyzed and their magnitude is analyzed by simulation. At the same time, the source of noise in the structure is analyzed, the Monte Carlo analysis method is introduced, and the influence of noise on the reading static noise tolerance of SRAM structure is analyzed by 2000 Monte Carlo simulations. In this paper, the power consumption, noise source and improvement of SRAM unit are studied, and a new single-terminal read asymmetrical 8-transistor SRAM cell structure is proposed. Then the composition and working principle of the new structure are introduced in detail, and its power consumption and noise source are analyzed. Finally, the power consumption and stability of the new 8 transistor cell are evaluated by comparing the performance of the standard 6 transistor SRAM cell. In this paper, the proposed new structure is supplemented by gated power supply technology, subthreshold voltage mechanism, dynamic power supply method and the use of double-gate transistors to further improve its power consumption and stability performance, and compare the results.
【學位授予單位】：浙江大學
【學位級別】：碩士
【學位授予年份】：2013
【分類號】：TP333.8

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本文編號：2510467