【摘要】：波束形成是陣列信號(hào)處理過(guò)程的一個(gè)重要步驟，通過(guò)對(duì)接收的陣列數(shù)據(jù)進(jìn)行線性組合處理得到指向某個(gè)方向的最大波束輸出。波束形成器的性能對(duì)聲納、雷達(dá)等系統(tǒng)定位精度、處理能力和抗干擾能力等具有關(guān)鍵作用。本論文針對(duì)成像聲納系統(tǒng)中波束形成器的關(guān)鍵部件——FFT處理器的功能特性，深入分析了FFT算法流程，引入CORDIC算法簡(jiǎn)化復(fù)數(shù)乘法操作，基于FPGA平臺(tái)設(shè)計(jì)實(shí)現(xiàn)了FFT處理器。經(jīng)過(guò)時(shí)序仿真和硬件測(cè)試，運(yùn)行速度達(dá)到90MHz，處理速度快，運(yùn)算精度高，滿足了成像聲納系統(tǒng)的需求。 論文分析了CORDIC算法及基2、基4時(shí)域FFT算法的基本原理和流程。將CORDIC算法和基4時(shí)域FFT算法結(jié)合起來(lái)，采用流水線技術(shù)，，設(shè)計(jì)并實(shí)現(xiàn)了基于CORDIC的FFT處理器。該FFT處理器使用5級(jí)蝶形算法，各級(jí)蝶形算法之間構(gòu)成流水線結(jié)構(gòu)，能夠完成1024點(diǎn)的FFT運(yùn)算。 為了滿足成像聲納系統(tǒng)可靠性需求，應(yīng)用基于VMM的功能驗(yàn)證技術(shù)，搭建分層次、可重用、自動(dòng)化的功能驗(yàn)證平臺(tái)。對(duì)所設(shè)計(jì)的FFT處理器進(jìn)行了較為完備的功能驗(yàn)證，完成了FFT處理器的系統(tǒng)級(jí)驗(yàn)證工作，代碼行覆蓋率達(dá)到100%，條件覆蓋率達(dá)到96.34%，狀態(tài)機(jī)覆蓋率達(dá)到100%，綜合評(píng)分達(dá)到97.67%，提高了FFT處理器的可靠性。
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圖片說(shuō)明：驗(yàn)證方法舉例
[Abstract]:Beamforming is an important step in the process of array signal processing. The maximum beam output pointing to a certain direction is obtained by linear combination of the received array data. The performance of beamformer plays a key role in the positioning accuracy, processing ability and anti-interference ability of Sonar, radar and other systems. In this paper, according to the functional characteristics of FFT processor, which is the key component of beamformer in imaging Sonar system, the FFT algorithm flow is deeply analyzed, the CORDIC algorithm is introduced to simplify the complex multiplication operation, and the FFT processor is designed and implemented based on FPGA platform. Through time sequence simulation and hardware test, the running speed reaches 90MHz, the processing speed is fast and the operation precision is high, which meets the requirements of imaging Sonar system. In this paper, the basic principle and flow chart of CORDIC algorithm and base 2, base 4 time domain FFT algorithm are analyzed. Combining CORDIC algorithm with base 4 time domain FFT algorithm, a FFT processor based on CORDIC is designed and implemented by using pipeline technology. The FFT processor uses 5-level butterfly algorithm, and the pipeline structure is formed between the butterfly algorithms at all levels, which can complete the FFT operation of 1024 points. In order to meet the reliability requirements of imaging Sonar system, the functional verification technology based on VMM is applied to build a hierarchical, reusable and automatic functional verification platform. The designed FFT processor is verified by a more complete function, and the system-level verification of FFT processor is completed. The code line coverage is 100%, the conditional coverage is 96.34%, the state machine coverage is 100%, and the comprehensive score is 97. 67%. The reliability of FFT processor is improved.
【學(xué)位授予單位】：哈爾濱工程大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP332

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