高速數(shù)傳基帶板及串行接口的設(shè)計
發(fā)布時間：2019-06-29 08:50
【摘要】：隨著嵌入式處理技術(shù)的快速發(fā)展和人們對信息高速實時性的進一步要求，給高性能嵌入式系統(tǒng)帶來了許多難題。在傳統(tǒng)的嵌入式系統(tǒng)中，提高處理器的速度能極大改善系統(tǒng)性能。但研究表明，總線頻率表征的CPU可用帶寬的增長相對于由時鐘頻率表征的CPU內(nèi)核性能的增長較慢，而且他們之間的差距正在逐步擴大。因此，提高處理器的處理速度對于系統(tǒng)性能提高的影響已經(jīng)很微弱了，而系統(tǒng)內(nèi)部不同模塊之間的通信速度已成為了限制高速嵌入式系統(tǒng)性能提高的重要因素。于是，為了解決以上的難題，同時滿足現(xiàn)在和未來高性能嵌入式系統(tǒng)需求，一種針對高性能嵌入式系統(tǒng)芯片間和板間互聯(lián)而設(shè)計的，可實現(xiàn)點對點操作、高效且具有很高可靠性和有效擁塞控制的高速互聯(lián)協(xié)議——RapidIO應(yīng)運而生。 針對嵌入式系統(tǒng)的需求以及傳統(tǒng)互連方式的局限性，RapidIO協(xié)議做了如下改進：提高打包效率，減小傳輸時延、簡化流控機制和協(xié)議，限制軟件復雜度，使得糾錯重傳機制乃至整個協(xié)議棧易于實現(xiàn)、支持多種速率傳輸模式和多種物理層技術(shù)，靈活且易于擴展等。 本文正是基于高性能嵌入式系統(tǒng)所面臨的高速互聯(lián)瓶頸以及RapidIO所體現(xiàn)出的優(yōu)越性，對RapidIO技術(shù)進行分析和研究工作，具體如下：首先，對串行RapidIO協(xié)議的研究背景以及現(xiàn)階段國內(nèi)外的發(fā)展狀況做簡要說明。其次，就RapidIO協(xié)議結(jié)構(gòu)進行深入研究。為了滿足靈活性和可擴展性的要求，RapidIO協(xié)議分為三層：邏輯層、傳輸層和物理層，這種層次結(jié)構(gòu)的最大特點是，修改任意層的事務(wù)類型都不會影響到其它層，緊接著說明搭建高速數(shù)傳基帶開發(fā)板平臺。最后，在這個硬件平臺上針對RapidIO協(xié)議，分別從端口的初始化、流量控制、錯誤管理等方面進行設(shè)計，實現(xiàn)FPGA芯片和DSP芯片間的高速串行互聯(lián)，說明RapidIO協(xié)議在現(xiàn)今高速數(shù)傳系統(tǒng)中的應(yīng)用并進行仿真驗證。通過理論分析和實驗結(jié)果可以看出，，相對于其他的互聯(lián)架構(gòu)，RapidIO在功能、性能等方面具有明顯的優(yōu)勢，是嵌入式系統(tǒng)互聯(lián)的最佳選擇之一。
[Abstract]:With the rapid development of embedded processing technology and the further requirements for high-speed real-time information, there are many problems for high-performance embedded systems. In the traditional embedded system, improving the speed of the processor can greatly improve the system performance. However, the research shows that the increase of available bandwidth of CPU represented by bus frequency is slower than that of CPU kernel characterized by clock frequency, and the gap between them is gradually widening. Therefore, the influence of improving the processing speed of the processor on the performance of the system is very weak, and the communication speed between different modules in the system has become an important factor limiting the performance improvement of the high-speed embedded system. Therefore, in order to solve the above problems and meet the needs of current and future high-performance embedded systems, a high-speed interconnection protocol, RapidIO, which can realize point-to-point operation and has high reliability and effective congestion control, is designed for the interconnection between chips and boards of high-performance embedded systems. In view of the requirements of embedded systems and the limitations of traditional interconnection methods, RapidIO protocol has made the following improvements: improving packaging efficiency, reducing transmission delay, simplifying flow control mechanism and protocol, limiting software complexity, making error correction retransmission mechanism and even the whole protocol stack easy to implement, supporting a variety of rate transmission modes and a variety of physical layer technologies, flexible and easy to expand, and so on. Based on the bottleneck of high-speed interconnection faced by high-performance embedded systems and the advantages of RapidIO, this paper analyzes and studies RapidIO technology as follows: firstly, the research background of serial RapidIO protocol and the development of serial RapidIO protocol at home and abroad are briefly described. Secondly, the structure of RapidIO protocol is deeply studied. In order to meet the requirements of flexibility and scalability, RapidIO protocol is divided into three layers: logic layer, transport layer and physical layer. the biggest characteristic of this hierarchical structure is that modifying the transaction type of any layer will not affect other layers, and then explains the construction of high-speed data transmission baseband development board platform. Finally, on this hardware platform, the RapidIO protocol is designed from the aspects of port initialization, flow control, error management and so on, and the high-speed serial interconnection between FPGA chip and DSP chip is realized. The application of RapidIO protocol in today's high-speed data transmission system is illustrated and verified by simulation. Through theoretical analysis and experimental results, it can be seen that RapidIO has obvious advantages in function and performance compared with other interconnection architecture, and it is one of the best options for embedded system interconnection.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2013
【分類號】：TP334.7
本文編號：2507698
[Abstract]:With the rapid development of embedded processing technology and the further requirements for high-speed real-time information, there are many problems for high-performance embedded systems. In the traditional embedded system, improving the speed of the processor can greatly improve the system performance. However, the research shows that the increase of available bandwidth of CPU represented by bus frequency is slower than that of CPU kernel characterized by clock frequency, and the gap between them is gradually widening. Therefore, the influence of improving the processing speed of the processor on the performance of the system is very weak, and the communication speed between different modules in the system has become an important factor limiting the performance improvement of the high-speed embedded system. Therefore, in order to solve the above problems and meet the needs of current and future high-performance embedded systems, a high-speed interconnection protocol, RapidIO, which can realize point-to-point operation and has high reliability and effective congestion control, is designed for the interconnection between chips and boards of high-performance embedded systems. In view of the requirements of embedded systems and the limitations of traditional interconnection methods, RapidIO protocol has made the following improvements: improving packaging efficiency, reducing transmission delay, simplifying flow control mechanism and protocol, limiting software complexity, making error correction retransmission mechanism and even the whole protocol stack easy to implement, supporting a variety of rate transmission modes and a variety of physical layer technologies, flexible and easy to expand, and so on. Based on the bottleneck of high-speed interconnection faced by high-performance embedded systems and the advantages of RapidIO, this paper analyzes and studies RapidIO technology as follows: firstly, the research background of serial RapidIO protocol and the development of serial RapidIO protocol at home and abroad are briefly described. Secondly, the structure of RapidIO protocol is deeply studied. In order to meet the requirements of flexibility and scalability, RapidIO protocol is divided into three layers: logic layer, transport layer and physical layer. the biggest characteristic of this hierarchical structure is that modifying the transaction type of any layer will not affect other layers, and then explains the construction of high-speed data transmission baseband development board platform. Finally, on this hardware platform, the RapidIO protocol is designed from the aspects of port initialization, flow control, error management and so on, and the high-speed serial interconnection between FPGA chip and DSP chip is realized. The application of RapidIO protocol in today's high-speed data transmission system is illustrated and verified by simulation. Through theoretical analysis and experimental results, it can be seen that RapidIO has obvious advantages in function and performance compared with other interconnection architecture, and it is one of the best options for embedded system interconnection.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2013
【分類號】：TP334.7
【參考文獻】
相關(guān)期刊論文 前2條
1 李宥謀;;8B/10B編碼器的設(shè)計及實現(xiàn)[J];電訊技術(shù);2005年06期
2 崔維嘉,樊少杰;新一代的總線結(jié)構(gòu)──RapidIO[J];通信技術(shù);2001年04期
本文編號：2507698
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