一種緩解多線程訪存干擾的VRB內(nèi)存機(jī)制
發(fā)布時(shí)間:2019-06-12 02:45
【摘要】:目前處理器通過(guò)持續(xù)增加核數(shù)和同時(shí)執(zhí)行的線程數(shù)來(lái)提高系統(tǒng)性能.但是,增加共享內(nèi)存的處理器核數(shù)和線程數(shù)會(huì)使得存儲(chǔ)器中的行緩存(row-buffer,RB)命中率下降,造成存儲(chǔ)器訪問(wèn)功耗增加和訪存延遲增加.設(shè)計(jì)并開(kāi)發(fā)了一種細(xì)粒度的victim row-buffer(VRB)內(nèi)存機(jī)制系統(tǒng)來(lái)解決此問(wèn)題.VRB機(jī)制提供附加的行緩存(VRB),暫時(shí)緩存由于行緩存(RB)沖突而從行緩存(RB)逐出的數(shù)據(jù),以備后續(xù)可能的訪問(wèn).這種機(jī)制緩解了多線程沖突,增加了DRAM中行緩存數(shù)據(jù)的重用率,避免了不必要的內(nèi)存數(shù)據(jù)陣列的訪問(wèn)、行激活和預(yù)充電、數(shù)據(jù)傳輸?shù)入娐穭?dòng)作,可以通過(guò)少量的硬件代價(jià)提高內(nèi)存系統(tǒng)的性能,并節(jié)約系統(tǒng)的功耗消耗.通過(guò)時(shí)序精確的全系統(tǒng)模擬器實(shí)驗(yàn),對(duì)比8核的Intel Xeon處理器,所提出的VRB機(jī)制可以達(dá)到最高17.6%(平均8.7%)的系統(tǒng)級(jí)吞吐率改善、最高142.9%(平均51.4%)的行緩存命中率改善以及最高17.6%(平均9.2%)的系統(tǒng)功耗改善.
[Abstract]:At present, the processor improves the system performance by continuously increasing the number of cores and the number of threads executed at the same time. However, increasing the number of processor cores and threads in shared memory will reduce the hit ratio of row cache (row-buffer,RB) in memory, resulting in the increase of memory access power consumption and memory access delay. A fine-granularity victim row-buffer (VRB) memory mechanism system is designed and developed to solve this problem. VRB mechanism provides additional row cache (VRB), temporary cache of data expelled from row cache (RB) due to row cache (RB) conflict for possible subsequent access. This mechanism alleviates multi-thread conflict, increases the reuse rate of row cache data in DRAM, avoids unnecessary access to memory data array, row activation and precharging, data transmission and other circuit actions, can improve the performance of memory system through a small amount of hardware cost, and save the power consumption of the system. Through the experiment of the whole system simulator with accurate timing, compared with the 8-core Intel Xeon processor, the proposed VRB mechanism can improve the system throughput by 17.6% (average 8.7%), the row cache hit ratio by 142.9% (average 51.4%) and the system power consumption by 17.6% (average 9.2%).
【作者單位】: 計(jì)算機(jī)體系結(jié)構(gòu)國(guó)家重點(diǎn)實(shí)驗(yàn)室(中國(guó)科學(xué)院計(jì)算技術(shù)研究所);中國(guó)科學(xué)院大學(xué);北京市移動(dòng)計(jì)算和新型終端重點(diǎn)實(shí)驗(yàn)室(中國(guó)科學(xué)院計(jì)算技術(shù)研究所);
【基金】:國(guó)家“九七三”重點(diǎn)基礎(chǔ)研究發(fā)展計(jì)劃基金項(xiàng)目(2011CB302501) 國(guó)家自然科學(xué)基金項(xiàng)目(61020106002,61221062) NSFC與香港RGC合作項(xiàng)目(61161160566) “核高基”國(guó)家科技重大專項(xiàng)基金項(xiàng)目(2013ZX0102-8001-001-001)
【分類號(hào)】:TP333
,
本文編號(hào):2497663
[Abstract]:At present, the processor improves the system performance by continuously increasing the number of cores and the number of threads executed at the same time. However, increasing the number of processor cores and threads in shared memory will reduce the hit ratio of row cache (row-buffer,RB) in memory, resulting in the increase of memory access power consumption and memory access delay. A fine-granularity victim row-buffer (VRB) memory mechanism system is designed and developed to solve this problem. VRB mechanism provides additional row cache (VRB), temporary cache of data expelled from row cache (RB) due to row cache (RB) conflict for possible subsequent access. This mechanism alleviates multi-thread conflict, increases the reuse rate of row cache data in DRAM, avoids unnecessary access to memory data array, row activation and precharging, data transmission and other circuit actions, can improve the performance of memory system through a small amount of hardware cost, and save the power consumption of the system. Through the experiment of the whole system simulator with accurate timing, compared with the 8-core Intel Xeon processor, the proposed VRB mechanism can improve the system throughput by 17.6% (average 8.7%), the row cache hit ratio by 142.9% (average 51.4%) and the system power consumption by 17.6% (average 9.2%).
【作者單位】: 計(jì)算機(jī)體系結(jié)構(gòu)國(guó)家重點(diǎn)實(shí)驗(yàn)室(中國(guó)科學(xué)院計(jì)算技術(shù)研究所);中國(guó)科學(xué)院大學(xué);北京市移動(dòng)計(jì)算和新型終端重點(diǎn)實(shí)驗(yàn)室(中國(guó)科學(xué)院計(jì)算技術(shù)研究所);
【基金】:國(guó)家“九七三”重點(diǎn)基礎(chǔ)研究發(fā)展計(jì)劃基金項(xiàng)目(2011CB302501) 國(guó)家自然科學(xué)基金項(xiàng)目(61020106002,61221062) NSFC與香港RGC合作項(xiàng)目(61161160566) “核高基”國(guó)家科技重大專項(xiàng)基金項(xiàng)目(2013ZX0102-8001-001-001)
【分類號(hào)】:TP333
,
本文編號(hào):2497663
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