一種緩解多線程訪存干擾的VRB內存機制
發(fā)布時間：2019-06-12 02:45
【摘要】：目前處理器通過持續(xù)增加核數(shù)和同時執(zhí)行的線程數(shù)來提高系統(tǒng)性能.但是,增加共享內存的處理器核數(shù)和線程數(shù)會使得存儲器中的行緩存(row-buffer,RB)命中率下降,造成存儲器訪問功耗增加和訪存延遲增加.設計并開發(fā)了一種細粒度的victim row-buffer(VRB)內存機制系統(tǒng)來解決此問題.VRB機制提供附加的行緩存(VRB),暫時緩存由于行緩存(RB)沖突而從行緩存(RB)逐出的數(shù)據(jù),以備后續(xù)可能的訪問.這種機制緩解了多線程沖突,增加了DRAM中行緩存數(shù)據(jù)的重用率,避免了不必要的內存數(shù)據(jù)陣列的訪問、行激活和預充電、數(shù)據(jù)傳輸?shù)入娐穭幼?可以通過少量的硬件代價提高內存系統(tǒng)的性能,并節(jié)約系統(tǒng)的功耗消耗.通過時序精確的全系統(tǒng)模擬器實驗,對比8核的Intel Xeon處理器,所提出的VRB機制可以達到最高17.6%(平均8.7%)的系統(tǒng)級吞吐率改善、最高142.9%(平均51.4%)的行緩存命中率改善以及最高17.6%(平均9.2%)的系統(tǒng)功耗改善.
[Abstract]:At present, the processor improves the system performance by continuously increasing the number of cores and the number of threads executed at the same time. However, increasing the number of processor cores and threads in shared memory will reduce the hit ratio of row cache (row-buffer,RB) in memory, resulting in the increase of memory access power consumption and memory access delay. A fine-granularity victim row-buffer (VRB) memory mechanism system is designed and developed to solve this problem. VRB mechanism provides additional row cache (VRB), temporary cache of data expelled from row cache (RB) due to row cache (RB) conflict for possible subsequent access. This mechanism alleviates multi-thread conflict, increases the reuse rate of row cache data in DRAM, avoids unnecessary access to memory data array, row activation and precharging, data transmission and other circuit actions, can improve the performance of memory system through a small amount of hardware cost, and save the power consumption of the system. Through the experiment of the whole system simulator with accurate timing, compared with the 8-core Intel Xeon processor, the proposed VRB mechanism can improve the system throughput by 17.6% (average 8.7%), the row cache hit ratio by 142.9% (average 51.4%) and the system power consumption by 17.6% (average 9.2%).
【作者單位】： 計算機體系結構國家重點實驗室(中國科學院計算技術研究所);中國科學院大學;北京市移動計算和新型終端重點實驗室(中國科學院計算技術研究所);
【基金】：國家“九七三”重點基礎研究發(fā)展計劃基金項目(2011CB302501) 國家自然科學基金項目(61020106002,61221062) NSFC與香港RGC合作項目(61161160566) “核高基”國家科技重大專項基金項目(2013ZX0102-8001-001-001)
【分類號】：TP333
，
本文編號：2497663
[Abstract]:At present, the processor improves the system performance by continuously increasing the number of cores and the number of threads executed at the same time. However, increasing the number of processor cores and threads in shared memory will reduce the hit ratio of row cache (row-buffer,RB) in memory, resulting in the increase of memory access power consumption and memory access delay. A fine-granularity victim row-buffer (VRB) memory mechanism system is designed and developed to solve this problem. VRB mechanism provides additional row cache (VRB), temporary cache of data expelled from row cache (RB) due to row cache (RB) conflict for possible subsequent access. This mechanism alleviates multi-thread conflict, increases the reuse rate of row cache data in DRAM, avoids unnecessary access to memory data array, row activation and precharging, data transmission and other circuit actions, can improve the performance of memory system through a small amount of hardware cost, and save the power consumption of the system. Through the experiment of the whole system simulator with accurate timing, compared with the 8-core Intel Xeon processor, the proposed VRB mechanism can improve the system throughput by 17.6% (average 8.7%), the row cache hit ratio by 142.9% (average 51.4%) and the system power consumption by 17.6% (average 9.2%).
【作者單位】： 計算機體系結構國家重點實驗室(中國科學院計算技術研究所);中國科學院大學;北京市移動計算和新型終端重點實驗室(中國科學院計算技術研究所);
【基金】：國家“九七三”重點基礎研究發(fā)展計劃基金項目(2011CB302501) 國家自然科學基金項目(61020106002,61221062) NSFC與香港RGC合作項目(61161160566) “核高基”國家科技重大專項基金項目(2013ZX0102-8001-001-001)
【分類號】：TP333
，
本文編號：2497663
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