RISC處理器中IMMU的設計與實現(xiàn)
發(fā)布時間：2019-05-28 19:58
【摘要】：IMMU (Instruction Memory Management Unit)指令存儲管理單元,是微處理器的一個重要組成部分。其作用在于完成從虛擬地址(virtual address)到物理地址(phusical address)的轉換,對存儲空間進行分配,對存儲信息進行保護,從而保證操作系統(tǒng)的有效運行。隨著大數(shù)據(jù)時代的到來,高通量計算系統(tǒng)越來越受到相關研究人員的關注。在這樣的背景下,作為微處理器的重要組成部分,IMMU需要不斷提高其有效操作的速度,減少器件運行中的功耗,同時,在保證IMMU性能的前提下,減少器件面積。針對以上問題,筆者對RISC(Reduced Instruction Set Computing)架構下處理器中的IMMU進行了相關研究,主要工作安排如下： 1.分析RISC架構下,IMMU的設計原理、存儲管理機制及快速地址訪問技術。針對IMMU設計的特點及存在的問題,同時,借鑒市場表現(xiàn)出色的處理器產品,完成對IMMU的方案設計。該IMMU支持多線程和流水級操作,其重要的組成部件包括ITLB(Instrution Translation Lookaside Buffer)和Hardware Translation Table Walk。這樣的設計架構,能夠有效地減少IMMU運行功耗,同時,提高器件完成有效操作的速度； 2. IMMU器件的工程設計與實現(xiàn)。在ITLB設計中,對SRAM的設計方案進行了改進,提高了ITLB器件的讀寫速度；Hardware Translation Table Walk采用硬件電路方式實現(xiàn),支持不同粒度的地址訪問。器件內部建立了完善的控制系統(tǒng)有效地避免了器件運行中的沖突問題,借助改進型的輪詢機制設計方法,設計出IMMU與其他器件之間的通信接口電路,在提高微處理器各器件之間的協(xié)調能力的前提下提升了IMMU的整體性能； 3. IMMU器件的仿真與驗證。一方面,利用synopsys設計軟件對IMMU器件進行寄存器傳輸級和網表級的邏輯驗證；另一方面,利用Xilinx XC7K325T FPGA芯片,進行FPGA原型驗證； 4. IMMU器件的性能評估。針對IMMU器件的工作頻率、面積和功耗等重要問題,分別從時序、面積和功耗三個角度,完成對設計器件性能的評估；本課題中,在65nm制造工藝下,IMMU器件能夠達到800MHz,與相同工藝水平的處理器芯片相比,該設計綜合面積占芯片總面積的0.75%,功耗占芯片總功耗的3.33%,結果比較可觀。因此,本課題研究工作對IMMU的設計工作具有很好的現(xiàn)實指導意義。
[Abstract]:IMMU (Instruction Memory Management Unit) instruction storage management unit is an important part of microprocessor. Its function is to complete the conversion from virtual address (virtual address) to physical address (phusical address), allocate storage space and protect storage information, so as to ensure the effective operation of the operating system. With the advent of big data era, high-throughput computing system has been paid more and more attention by relevant researchers. In this context, as an important part of microprocessor, IMMU needs to improve the speed of its effective operation, reduce the power consumption in the operation of the device, and reduce the device area under the premise of ensuring the performance of IMMU. In view of the above problems, the author has carried on the related research to the IMMU in the RISC (Reduced Instruction Set Computing) architecture, the main work arrangement is as follows: 1. The design principle, storage management mechanism and fast address access technology of IMMU under RISC architecture are analyzed. According to the characteristics and existing problems of IMMU design, the scheme design of IMMU is completed by drawing lessons from the processor products with excellent market performance. The IMMU supports multithreading and flow-level operations, and its important components include ITLB (Instrution Translation Lookaside Buffer) and Hardware Translation Table Walk. Such a design architecture can effectively reduce the power consumption of IMMU, at the same time, improve the speed of the device to complete the effective operation; 2. Engineering design and implementation of IMMU devices. In the design of ITLB, the design scheme of SRAM is improved, and the reading and writing speed of ITLB device is improved.; Hardware Translation Table Walk is realized by hardware circuit and supports address access with different granularity. A perfect control system is established to effectively avoid the conflict in the operation of the device. With the help of the improved polling mechanism design method, the communication interface circuit between IMMU and other devices is designed. On the premise of improving the coordination ability of each device of the microprocessor, the overall performance of IMMU is improved. 3. Simulation and verification of IMMU devices. On the one hand, using synopsys design software to verify the register transmission level and network table level of IMMU devices; on the other hand, using Xilinx XC7K325T FPGA chip to verify the FPGA prototype; 4. Performance evaluation of IMMU devices. Aiming at the important problems such as working frequency, area and power consumption of IMMU devices, the performance of the designed devices is evaluated from three aspects: timing, area and power consumption. In this paper, under the 65nm manufacturing process, the IMMU device can reach 800MHz. Compared with the processor chip at the same process level, the comprehensive area of the design accounts for 0.75% of the total chip area and the power consumption accounts for 3.33% of the total power consumption of the chip. The results are considerable. Therefore, the research work of this subject has a good practical guiding significance for the design of IMMU.
【學位授予單位】：武漢理工大學
【學位級別】：碩士
【學位授予年份】：2013
【分類號】：TP332
[Abstract]:IMMU (Instruction Memory Management Unit) instruction storage management unit is an important part of microprocessor. Its function is to complete the conversion from virtual address (virtual address) to physical address (phusical address), allocate storage space and protect storage information, so as to ensure the effective operation of the operating system. With the advent of big data era, high-throughput computing system has been paid more and more attention by relevant researchers. In this context, as an important part of microprocessor, IMMU needs to improve the speed of its effective operation, reduce the power consumption in the operation of the device, and reduce the device area under the premise of ensuring the performance of IMMU. In view of the above problems, the author has carried on the related research to the IMMU in the RISC (Reduced Instruction Set Computing) architecture, the main work arrangement is as follows: 1. The design principle, storage management mechanism and fast address access technology of IMMU under RISC architecture are analyzed. According to the characteristics and existing problems of IMMU design, the scheme design of IMMU is completed by drawing lessons from the processor products with excellent market performance. The IMMU supports multithreading and flow-level operations, and its important components include ITLB (Instrution Translation Lookaside Buffer) and Hardware Translation Table Walk. Such a design architecture can effectively reduce the power consumption of IMMU, at the same time, improve the speed of the device to complete the effective operation; 2. Engineering design and implementation of IMMU devices. In the design of ITLB, the design scheme of SRAM is improved, and the reading and writing speed of ITLB device is improved.; Hardware Translation Table Walk is realized by hardware circuit and supports address access with different granularity. A perfect control system is established to effectively avoid the conflict in the operation of the device. With the help of the improved polling mechanism design method, the communication interface circuit between IMMU and other devices is designed. On the premise of improving the coordination ability of each device of the microprocessor, the overall performance of IMMU is improved. 3. Simulation and verification of IMMU devices. On the one hand, using synopsys design software to verify the register transmission level and network table level of IMMU devices; on the other hand, using Xilinx XC7K325T FPGA chip to verify the FPGA prototype; 4. Performance evaluation of IMMU devices. Aiming at the important problems such as working frequency, area and power consumption of IMMU devices, the performance of the designed devices is evaluated from three aspects: timing, area and power consumption. In this paper, under the 65nm manufacturing process, the IMMU device can reach 800MHz. Compared with the processor chip at the same process level, the comprehensive area of the design accounts for 0.75% of the total chip area and the power consumption accounts for 3.33% of the total power consumption of the chip. The results are considerable. Therefore, the research work of this subject has a good practical guiding significance for the design of IMMU.
【學位授予單位】：武漢理工大學
【學位級別】：碩士
【學位授予年份】：2013
【分類號】：TP332
【共引文獻】
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