兩端口EHCI設(shè)計及內(nèi)嵌模式下API接口的實現(xiàn)
[Abstract]:EHCI (Enhanced Host Controller, enhanced host control interface is an international standard host interface under USB (Universal Serial Bus, version 2.0 protocol, which has been widely used in the market. There are three main purposes of this study. One is to design a version of EHCI, with faster transmission speed and infinitely close to the theoretical value 480Mb/s through Verilog hardware design language, and the other is to realize two on-line transmission interfaces. The third is to add additional registers to the design, and then design the API (Application Programming Interface, application programming interface with C language on the basis of using these registers) interface, by using API interface, The system can control EHCI transmission without using standard EHCI driver. The first step of this study is architecture planning. In this paper, we systematically describe how to calculate the important parameters in the design according to the design objectives, including the size of FIFO, the depth of pipe-line and other important parameters. After determining the parameters, the function and implementation of each module are planned, such as the clock field in which each module is located, how to coordinate between modules, and how to deal with the problem of penetration frequency. Then, according to the previous planning to implement RTL code, in the implementation of RTL code, we need to strictly abide by the code style to ensure that the code can be integrated into a network table. Then it is verified by simulation, the environment of this simulation is realized by UVM (Universal Verification Methodology, general verification method), the test content is comprehensive and the efficiency is high. At the end of the simulation work, the FPGA test and the implementation of API interface code are carried out synchronously, and the code of API interface is tested on FPGA. The last step is to test the transmission speed of EHCI in the simulation environment and to determine the area of EHCI by synthesizing the code. Through this design, it can be confirmed that in fact, the transmission speed of EHCI can reach 416MB / s, which is close to the theoretical value of 480MB / s, and the speed of EHCI tested on the market is about 300Mb/s. There are two prerequisites for achieving such a transmission speed. One is that the driver does not put useless transmission control packets into the transmission list as far as possible, and the transmission volume of each transmission reaches the maximum value as much as possible. On the other hand, it is necessary to carry out peer-to-peer transmission equipment fast enough to reflect the speed advantage of host EHCI. One of the effects of the increase in speed is the increase in area, which is twice as large as that of some old versions of EHCI. Assuming that the EHCI on the market is a reasonable equilibrium point between speed and area, this design is to put aside the pursuit speed of this equilibrium point, and the result is that the speed is increased by 30% and the area is increased by 100%.
【學(xué)位授予單位】:電子科技大學(xué)
【學(xué)位級別】:碩士
【學(xué)位授予年份】:2014
【分類號】:TP334.7
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