【摘要】：可重構(gòu)計算通過在時空域上重用硬件資源完成計算任務(wù),在可重構(gòu)系統(tǒng)中,硬件任務(wù)可以像軟件程序一樣動態(tài)的調(diào)用和修改,既保留了硬件的計算性能,又具備了軟件的靈活性。隨著以圖像處理、數(shù)字信號處理為代表的數(shù)據(jù)流計算應(yīng)用日趨廣泛,如何使得編程人員根據(jù)具體的應(yīng)用需求動態(tài)配置相應(yīng)的功能,并通過不同類型的并行性發(fā)掘、兼顧數(shù)據(jù)流處理的高效能和配置靈活性,是目前可重構(gòu)系統(tǒng)面臨的兩個主要問題。 針對上述問題,本文以面向數(shù)據(jù)流的硬件任務(wù)接口設(shè)計、可重構(gòu)流處理結(jié)構(gòu)設(shè)計為出發(fā)點(diǎn),完成了以下研究工作： 1、針對數(shù)據(jù)流處理,設(shè)計并實(shí)現(xiàn)了基于總線的統(tǒng)一的流接口。利用數(shù)據(jù)流驅(qū)動計算特征,為用戶硬件任務(wù)提供基于總線的統(tǒng)一的流接口以及對應(yīng)的編程API(Application Programming Interface)。上述接口設(shè)計支持硬件任務(wù)的高性能處理,還對系統(tǒng)編程人員屏蔽底層設(shè)計細(xì)節(jié),便于實(shí)現(xiàn)硬件任務(wù)的統(tǒng)一管理和靈活調(diào)度。 2、針對基于總線的流接口存在的帶寬瓶頸、CPU占用率高等不足,設(shè)計并實(shí)現(xiàn)了基于LocalLink的統(tǒng)一的流接口。該接口利用同步的、點(diǎn)對點(diǎn)的數(shù)據(jù)流通信接口協(xié)議,使得數(shù)據(jù)流通信連接關(guān)系可根據(jù)任務(wù)之間的數(shù)據(jù)依賴關(guān)系進(jìn)行動態(tài)配置,克服了傳統(tǒng)片上系統(tǒng)總線的通信瓶頸,并能夠顯著降低CPU利用率。經(jīng)測試,硬件任務(wù)與軟件任務(wù)之間的通信帶寬可達(dá)到800Mbps,硬件任務(wù)與硬件任務(wù)之間的通信帶寬可達(dá)到800Mbps。 3、以FPGA為數(shù)據(jù)流處理平臺,設(shè)計并實(shí)現(xiàn)了功能和互連可動態(tài)重構(gòu)的高效能片上系統(tǒng)(System-on-Chip, SoC)。通過部分動態(tài)重構(gòu)技術(shù)實(shí)現(xiàn)功能重構(gòu),通過交叉開關(guān)矩陣實(shí)現(xiàn)任務(wù)間互連關(guān)系重構(gòu),從而靈活地支持多種數(shù)據(jù)流計算模式,發(fā)掘不同種類的并行。實(shí)驗(yàn)結(jié)果表明,與已有基于FPGA的片上系統(tǒng)實(shí)現(xiàn)相比,AES、DES、DCT處理功耗效能有顯著提升,該結(jié)構(gòu)便于用戶根據(jù)應(yīng)用需要配置相應(yīng)的數(shù)據(jù)流計算模式,降低了設(shè)計難度,并充分發(fā)揮了可重構(gòu)系統(tǒng)的高效性和靈活性。
[Abstract]:Reconfigurable computing completes computing tasks by reusing hardware resources in space-time domain. In reconfigurable systems, hardware tasks can be called and modified as dynamically as software programs, which not only preserves the computing performance of hardware. It also has the flexibility of software. With the increasing application of data stream computing represented by image processing and digital signal processing, how to make programmers dynamically configure the corresponding functions according to the specific application requirements, and through different types of parallelism mining, Taking into account the high efficiency and configuration flexibility of data flow processing are the two main problems faced by reconfigurable systems at present. In order to solve the above problems, this paper takes the design of data flow oriented hardware task interface and restructured flow processing structure as the starting point, and completes the following research work: 1, for data flow processing, A unified flow interface based on bus is designed and implemented. Using data flow driven computing characteristics to provide a unified bus-based flow interface for user hardware tasks and the corresponding programming API (Application Programming Interface). The above interface design supports the high performance processing of hardware tasks, and also shielded the underlying design details for system programmers, which is convenient to realize the unified management and flexible scheduling of hardware tasks. 2. Aiming at the bandwidth bottleneck of bus-based stream interface and the high utilization rate of CPU, a unified flow interface based on LocalLink is designed and implemented. The interface makes use of the synchronous, point-to-point data flow communication interface protocol, so that the data flow communication connection relationship can be dynamically configured according to the data dependence between tasks, and the communication bottleneck of the traditional system bus on the chip is overcome. It can significantly reduce the utilization rate of CPU. After testing, the communication bandwidth between hardware task and software task can reach 800Mbps, and the communication bandwidth between hardware task and hardware task can reach 800Mbps. 3. Using FPGA as the data flow processing platform, an efficient energy-on-chip system (System-on-Chip, SoC).) with dynamic refactoring function and interconnection is designed and implemented. The functional reconstruction is realized by partial dynamic reconstruction technology, and the interconnection relationship between tasks is reconstructed by cross-switching matrix, so as to flexibly support a variety of data flow computing patterns and discover different kinds of parallelism. The experimental results show that compared with the existing on-chip system implementation based on FPGA, the power consumption efficiency of AES,DES,DCT processing is significantly improved. The structure is convenient for users to configure the corresponding data flow calculation mode according to the application needs, and reduces the design difficulty. The efficiency and flexibility of the reconfigurable system are brought into full play.
【學(xué)位授予單位】：復(fù)旦大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP334.7

【共引文獻(xiàn)】

相關(guān)期刊論文 前2條

1 孫兆偉;劉源;邢雷;徐國棟;;面向多任務(wù)的可重構(gòu)星載計算機(jī)設(shè)計[J];系統(tǒng)工程與電子技術(shù);2011年06期

2 陳乃金;江建慧;陳昕;周洲;徐瑩;潘誠;;動態(tài)可重構(gòu)系統(tǒng)的時域劃分及其行為級算法的定量分析[J];小型微型計算機(jī)系統(tǒng);2011年02期

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本文編號：2483784