AMD-APU的內(nèi)存控制器的測試技術(shù)研究和改進(jìn)
發(fā)布時間：2019-05-18 07:15
【摘要】：作為電腦的重要組成部件，內(nèi)存的進(jìn)化和發(fā)展一直影響著電腦的運算速度和整體性能，雖然市場上最快內(nèi)存DDR3的最高數(shù)據(jù)傳輸速率已經(jīng)可以達(dá)到2133MT/s，但是配置最快的DDR3并不能夠保證最高的運算速度，因為系統(tǒng)性能會被另外一個重要參數(shù)“內(nèi)存延遲”影響。內(nèi)存延遲是指外置內(nèi)存管理器必須通過北橋進(jìn)行內(nèi)存與處理器之間的數(shù)據(jù)傳輸從而帶來的傳輸延遲。為了可以充分發(fā)揮內(nèi)存的高速數(shù)據(jù)傳輸能力AMD從K8系列CPU（包括Socket754/939/940等接口的各種處理器）內(nèi)部開始整合了內(nèi)存控制器，就可以有效控制內(nèi)存控制器工作在與處理器核心同樣的頻率上，而且由于內(nèi)存與處理器之間的數(shù)據(jù)傳輸無需經(jīng)過北橋，可以有效降低傳輸延遲，這個內(nèi)置內(nèi)存管理器簡稱為DDR。作為AMD最新的APU產(chǎn)品，市場匹配最高速的內(nèi)存，為了滿足客戶的高性能要求，DDR的質(zhì)量是極為重要部分。 APU是AMD最新主推的集成中央處理器CPU和顯卡GPU的芯片，其內(nèi)部的內(nèi)存控制器功能比K8系列產(chǎn)品更加強(qiáng)勁，，可以支持市面上最快的DDR內(nèi)存。AMD蘇州作為最重要的測試站點致力于有效迅速地判斷產(chǎn)品優(yōu)劣，在保證客戶質(zhì)量的同時有效控制生產(chǎn)成本。測試的內(nèi)容包括了已有的大多數(shù)基礎(chǔ)測試，重點是如何確定適合APU的測試條件，然后才可以開始大批量測試。測試條件的選定決定了AMD的測試結(jié)果和客戶拿到的產(chǎn)品質(zhì)量，也決定了測試結(jié)果能否正確反映出前端生產(chǎn)的問題。選定測試條件需要進(jìn)行產(chǎn)品特性描述，是半導(dǎo)體測試推出中重要的部分，本文會著重介紹基于APU的特性描述的過程，包括制定計劃、實施過程、數(shù)據(jù)分析和最終決定。 產(chǎn)品特性描述的重要性在于選擇的測試條件使得測試的誤差最小，但是測試硬件的差異性，產(chǎn)品本身特性的波動和測試軟件的程序缺陷還是會造成測試的誤差。這個誤差的表現(xiàn)通常體現(xiàn)在測試不良率上。及時發(fā)現(xiàn)測試不良率的變化然后做出改進(jìn)是AMD產(chǎn)品穩(wěn)定測試和順利提供給客戶產(chǎn)品的保證。本文會介紹幾種不同類型的案例，從問題發(fā)現(xiàn)、分析和解決的角度介紹測試內(nèi)容的改進(jìn)過程。與研究或設(shè)計遇到的問題解決方式不同，整個過程不光著重于技術(shù)層面的研究，更重要的是基于大批量測試的分析手法和改進(jìn)方案。 綜上所述，本文介紹了基于AMD APU內(nèi)存控制器的測試發(fā)布和改進(jìn)的整個過程，包括測試內(nèi)容的制定和發(fā)布，產(chǎn)品特性描述和基于大批量測試結(jié)果的改進(jìn)。
[Abstract]:As an important component of the computer, the evolution and development of memory has been affecting the computing speed and overall performance of the computer, although the highest data transmission rate of the fastest memory DDR3 on the market has reached 2133 MTS. However, the fastest configuration of DDR3 does not guarantee the highest computing speed, because system performance will be affected by another important parameter, "memory delay". Memory delay refers to the transmission delay caused by the data transmission between memory and processor that the external memory manager must carry out through the north bridge. In order to give full play to the high-speed data transmission capability of memory AMD began to integrate memory controllers from within the K8 series CPU (including various processors of interfaces such as Socket754/939/940). It can effectively control the memory controller to work at the same frequency as the processor core, and because the data transmission between memory and processor does not need to pass through the North Bridge, it can effectively reduce the transmission delay. This built-in memory manager is referred to as DDR. for short. As the latest APU product of AMD, the market matches the highest speed memory. In order to meet the high performance requirements of customers, the quality of DDR is a very important part. APU is AMD's latest integrated CPU and graphics card GPU chip, and its internal memory controller is more powerful than the K8 family of products. It can support the fastest DDR memory on the market. Amd Suzhou, as the most important test site, is committed to effectively and quickly judging the quality of products and effectively controlling the production cost while ensuring customer quality. The content of the test includes most of the existing basic tests, focusing on how to determine the test conditions suitable for APU before you can start mass testing. The selection of test conditions determines the test results of AMD and the product quality obtained by customers, and also determines whether the test results can correctly reflect the problems of front-end production. The selection of test conditions requires product characteristic description, which is an important part of semiconductor test roll-out. This paper focuses on the process of APU-based feature description, including planning, implementation process, data analysis and final decision. The importance of product characteristic description lies in the fact that the test error is minimized by the selected test conditions, but the difference of test hardware, the fluctuation of product's own characteristics and the program defect of test software will still cause the error of test. The performance of this error is usually reflected in the poor test rate. Timely detection of test failure rate changes and then make improvements is the guarantee of AMD product stability testing and smooth provision to customers. This paper introduces several different types of cases, and introduces the improvement process of test content from the point of view of problem discovery, analysis and solution. Different from the problem solving methods encountered in the research or design, the whole process not only focuses on the technical research, but also on the analysis method and improvement scheme based on mass testing. To sum up, this paper introduces the whole process of test release and improvement based on AMD APU memory controller, including the formulation and release of test content, product feature description and improvement based on mass test results.
【學(xué)位授予單位】：蘇州大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP333
本文編號：2479783
[Abstract]:As an important component of the computer, the evolution and development of memory has been affecting the computing speed and overall performance of the computer, although the highest data transmission rate of the fastest memory DDR3 on the market has reached 2133 MTS. However, the fastest configuration of DDR3 does not guarantee the highest computing speed, because system performance will be affected by another important parameter, "memory delay". Memory delay refers to the transmission delay caused by the data transmission between memory and processor that the external memory manager must carry out through the north bridge. In order to give full play to the high-speed data transmission capability of memory AMD began to integrate memory controllers from within the K8 series CPU (including various processors of interfaces such as Socket754/939/940). It can effectively control the memory controller to work at the same frequency as the processor core, and because the data transmission between memory and processor does not need to pass through the North Bridge, it can effectively reduce the transmission delay. This built-in memory manager is referred to as DDR. for short. As the latest APU product of AMD, the market matches the highest speed memory. In order to meet the high performance requirements of customers, the quality of DDR is a very important part. APU is AMD's latest integrated CPU and graphics card GPU chip, and its internal memory controller is more powerful than the K8 family of products. It can support the fastest DDR memory on the market. Amd Suzhou, as the most important test site, is committed to effectively and quickly judging the quality of products and effectively controlling the production cost while ensuring customer quality. The content of the test includes most of the existing basic tests, focusing on how to determine the test conditions suitable for APU before you can start mass testing. The selection of test conditions determines the test results of AMD and the product quality obtained by customers, and also determines whether the test results can correctly reflect the problems of front-end production. The selection of test conditions requires product characteristic description, which is an important part of semiconductor test roll-out. This paper focuses on the process of APU-based feature description, including planning, implementation process, data analysis and final decision. The importance of product characteristic description lies in the fact that the test error is minimized by the selected test conditions, but the difference of test hardware, the fluctuation of product's own characteristics and the program defect of test software will still cause the error of test. The performance of this error is usually reflected in the poor test rate. Timely detection of test failure rate changes and then make improvements is the guarantee of AMD product stability testing and smooth provision to customers. This paper introduces several different types of cases, and introduces the improvement process of test content from the point of view of problem discovery, analysis and solution. Different from the problem solving methods encountered in the research or design, the whole process not only focuses on the technical research, but also on the analysis method and improvement scheme based on mass testing. To sum up, this paper introduces the whole process of test release and improvement based on AMD APU memory controller, including the formulation and release of test content, product feature description and improvement based on mass test results.
【學(xué)位授予單位】：蘇州大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP333
【參考文獻(xiàn)】
相關(guān)期刊論文 前6條
1 劉冠男;歐明雙;宋何娟;;DDR2 SDRAM控制器的設(shè)計及FPGA驗證[J];中國集成電路;2010年04期
2 須文波;胡丹;;DDR2 SDRAM控制器的FPGA實現(xiàn)[J];江南大學(xué)學(xué)報;2006年02期
3 程曉東,鄭為民,唐志敏;基于DDR SDRAM控制器時序分析的模型[J];計算機(jī)工程;2005年17期
4 江先陽;劉新春;張佩珩;孫凝暉;徐志偉;;計算密集型體系集成DDR SDRAM控制器設(shè)計[J];計算機(jī)工程與科學(xué);2006年03期
5 ;Reliable Memory Feedback Design for a Class of Nonlinear Fuzzy Systems with Time-varying Delay[J];International Journal of Automation & Computing;2007年02期
6 張凱,李云崗;基于AMBA總線的DDR2 SDRAM控制器研究與實現(xiàn)[J];微電子學(xué)與計算機(jī);2005年09期
本文編號：2479783
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