集成電路設(shè)計中乘法器的低功耗算法與實現(xiàn)技術(shù)研究
發(fā)布時間：2019-04-02 09:34
【摘要】：在集成電路的設(shè)計中,功耗問題已經(jīng)成為這一領(lǐng)域內(nèi)除面積、速度外要慎重考慮的重要因素。當前,功耗低的設(shè)計基本上是從電路的基本構(gòu)成因素入手,設(shè)計時在不同環(huán)節(jié)都使用不同設(shè)計,進而使系統(tǒng)的功耗得到降低,以便盡可能取得最大的低功耗。
[Abstract]:In the design of integrated circuits, power consumption has become an important factor in this field besides area and speed. At present, the design of low power consumption is based on the basic components of the circuit. Different designs are used in different parts of the design, so that the power consumption of the system can be reduced, so that the maximum low power consumption can be obtained as far as possible.
【作者單位】： 合肥工業(yè)大學;
【分類號】：TP332.22
，
本文編號：2452454
[Abstract]:In the design of integrated circuits, power consumption has become an important factor in this field besides area and speed. At present, the design of low power consumption is based on the basic components of the circuit. Different designs are used in different parts of the design, so that the power consumption of the system can be reduced, so that the maximum low power consumption can be obtained as far as possible.
【作者單位】： 合肥工業(yè)大學;
【分類號】：TP332.22
，
本文編號：2452454
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