【摘要】：隨著集成電路設(shè)計和制造技術(shù)的發(fā)展，芯片設(shè)計內(nèi)部的規(guī)模也不斷的變大，性能要求也不斷的提高，使得單核已經(jīng)逐步被多核所逐漸取代，軟件上的程序設(shè)計也從串行程序設(shè)計到多線程程序開發(fā)，，隨之而來的問題是調(diào)試變得越來越復(fù)雜，另外芯片市場競爭也變得越來越激烈，面對上市時間的巨大壓力，實現(xiàn)一個穩(wěn)定、高效的系統(tǒng)需要有效的軟硬件調(diào)試方法變得尤為重要，如何縮短調(diào)試時間、提高調(diào)試速度對縮短SOC芯片的上市時間取決定性的意義。 本論文的主要研究工作是面向PACDSP CORE的多核調(diào)試控制器硬件設(shè)計與軟件驗證進(jìn)行研究。論文詳細(xì)的介紹了該調(diào)試控制器的硬件和軟件部分，首先對于硬件內(nèi)部的各個模塊進(jìn)行了詳細(xì)的介紹，及其內(nèi)部電路是如何實現(xiàn)的也作了詳細(xì)的說明；然后對軟件部分的斷點種類進(jìn)行介紹，如何設(shè)置/移除，所用調(diào)試工具及其支援的命令集有一一進(jìn)行描述。 本文的整個操作流程是從PC機上的gdb窗口輸入能支援的命令開始，軟件部分主要是對這些命令進(jìn)行解析，解析完畢后，執(zhí)行相對應(yīng)的功能，然后通過調(diào)用USB驅(qū)動，按照USB協(xié)議將這些信息傳送給probe上的CYPRESS公司CY7C68013A芯片，該芯片會解析USB數(shù)據(jù)，并將解析出的信息寫到它的slaveFIFO，然后probe會處理將這些信息反映到JTAG_WRAP上，Probe再透過JTAG接口與PACDSP內(nèi)部的EICE電路進(jìn)行信息交換，從而達(dá)到調(diào)試PACDSP的目的。 本文的最后有介紹如何進(jìn)行仿真調(diào)試，從硬件的連接到軟件的調(diào)試都有一一進(jìn)行說明，其中硬件部分所需要的兩塊電路板，其中一塊為probe部分，另外一塊為EICE部分(除了EICE外，內(nèi)嵌有兩顆PACDSP CORE)，并有對軟件部分如何使用進(jìn)行說明。 硬件線路連接好后，在PC機上透過gdb窗口輸入命令，對所支援的命令逐一進(jìn)行調(diào)試，都能達(dá)到預(yù)期的效果。
[Abstract]:With the development of IC design and manufacturing technology, the internal scale of chip design is also increasing, and the performance requirements are constantly improved, so that single core has been gradually replaced by multi-core. Software programming also from serial programming to multi-thread program development, followed by the problem is that debugging becomes more and more complex, in addition, the chip market competition has become more and more fierce, facing the huge pressure of time to market, In order to achieve a stable and efficient system, it is very important to use effective hardware and software debugging methods. How to shorten debugging time and how to improve debugging speed are of great significance to shorten the time to market of SOC chips. The main research work of this thesis is the hardware design and software verification of PACDSP CORE-oriented multi-core debug controller. The hardware and software parts of the debugging controller are introduced in detail. Firstly, the modules inside the hardware are introduced in detail, and how to realize the internal circuit is also explained in detail. Then the types of breakpoints in the software part are introduced, how to set / remove, and the debugging tools used and the command sets supported are described one by one. The whole operation flow of this paper starts from the gdb window on the PC to input the commands that can be supported. In the software part, the commands are parsed. After the parsing, the corresponding functions are executed, and then the USB driver is used. According to the USB protocol, this information is transmitted to the CYPRESS company CY7C68013A chip on the probe, which parses the USB data, writes the parsed information to its slaveFIFO, and probe processes the information to reflect the information on the JTAG_WRAP. Probe exchanges information with EICE circuit in PACDSP through JTAG interface, so as to debug PACDSP. At the end of this paper, we introduce how to do simulation debugging. From hardware connection to software debugging, there are two circuit boards, one of which is probe and the other is EICE (except EICE). Embedded with two PACDSP CORE), and instructions on how to use the software section. After the hardware circuit is connected, the commands can be inputted through the gdb window on PC, and the supported commands can be debugged one by one, which can achieve the desired effect.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP332

【參考文獻(xiàn)】

相關(guān)期刊論文 前6條

1 慈艷柯,陳秀英,吳孫桃,郭東輝;片上系統(tǒng)的設(shè)計技術(shù)及其研究進(jìn)展[J];半導(dǎo)體技術(shù);2001年07期

2 薛嚴(yán)冰,徐曉軒;基于IP的系統(tǒng)芯片(SOC)設(shè)計[J];信息技術(shù);2004年10期

3 黃安文;高軍;張民選;;多核處理器片上存儲系統(tǒng)研究[J];計算機工程;2010年04期

4 唐杉;徐強;丁煒;;基于NoC的SoC中實時跟蹤數(shù)據(jù)的傳輸[J];計算機工程;2008年15期

5 彭保,范婷婷,馬建國;基于Verilog HDL語言的FPGA設(shè)計[J];微計算機信息;2004年10期

6 虞致國;魏敬和;;基于JTAG的SoC軟硬件協(xié)同驗證平臺設(shè)計[J];微電子學(xué)與計算機;2010年10期

本文編號：2450565