SRAM IP實速測試系統(tǒng)設(shè)計與測試
發(fā)布時間：2019-02-16 08:20
【摘要】：隨著集成電路特征尺寸不斷減小和電路工作頻率的不斷提高,存儲器故障不再是簡單的功能故障,由于電路的微弱延時引起的性能故障也成為了集成電路設(shè)計和測試中必須考慮的問題。本文以存儲器內(nèi)建自測試技術(shù)作為基礎(chǔ),研究靜態(tài)隨機存儲器SRAM實速測試芯片的設(shè)計及測試,提出了一種基于改進的算法設(shè)計的BIST系統(tǒng),并利用止(?)BIST擴展設(shè)計了實速測試系統(tǒng),同時分析了存儲器實速測試的原理,以所設(shè)計的實速測試芯片對SRAM IP進行了測試。 SRAM實速測試的測試對象是SRAM IP的功能測試和性能測試。對于功能測試,本文首先分析了存儲器常見的故障類型,研究了幾種普遍采用的存儲器測試算法,在此基礎(chǔ)上提出了一種由改進March C+算法和棋盤法測試結(jié)合的測試圖形產(chǎn)生機制,改進后的算法可以有效地檢測傳統(tǒng)March C算法不能檢測的耦合失效和臨近圖形敏感失效。基于改進的算法,以自頂向下的理念設(shè)計了內(nèi)建自測試電路并予以硬件實現(xiàn)和仿真,仿真結(jié)果標明所設(shè)計的BIST能夠在多數(shù)據(jù)背景下以較快速度遍歷。所設(shè)計的BIST電路實現(xiàn)了較高的故障檢查覆蓋率和較快的測試速度,具有良好的復(fù)用性。 對于SRAM的性能測試,本文對所設(shè)計的BIST進行擴展,加入全數(shù)字鎖相環(huán)和延時鏈電路。利用ADPLL產(chǎn)生的高頻時鐘和片外可調(diào)選項提供芯片模擬用戶使用的多頻率測試環(huán)境,利用延時電路和片外可調(diào)選項量取SRAM的存取時間等性能參數(shù)。本文對實速測試芯片量取SRAM性能參數(shù)的原理和測試過程做了詳盡敘述,并在25℃TT工藝角400MHz至設(shè)計預(yù)仿真值頻率的測試環(huán)境下對實速測試芯片進行測試。最后將所測試結(jié)果與SRAM設(shè)計師的預(yù)仿真值進行比較,得出所設(shè)計的實速測試芯片功能和性能都達到了設(shè)計規(guī)范中制定的設(shè)計指標。 實速測試芯片已經(jīng)以55nm SPRVT1P10M low-K工藝流片交付使用,已用于寄存器文件型單端口SRAM IP的測試。封裝類型是QFP100。
[Abstract]:With the decreasing of IC feature size and the increasing of circuit working frequency, the memory fault is no longer a simple functional fault. The performance failure caused by the weak delay of the circuit has also become a problem that must be considered in the design and testing of integrated circuits. Based on memory built-in self-test technology, this paper studies the design and test of SRAM real speed test chip for static random access memory, and proposes a BIST system based on improved algorithm design. The real speed testing system is designed by using the BIST extension, and the principle of memory real speed testing is analyzed. The SRAM IP is tested with the designed real speed test chip. The test object of SRAM real-speed test is the function test and performance test of SRAM IP. For function testing, this paper first analyzes the common fault types of memory, and studies several commonly used memory testing algorithms. On this basis, a test graph generation mechanism combining improved March C algorithm and chessboard test is proposed. The improved algorithm can effectively detect coupling failure and near graph sensitive failure that can not be detected by traditional March C algorithm. Based on the improved algorithm, the built-in self-test circuit is designed with the top-down idea, and the hardware implementation and simulation are given. The simulation results show that the designed BIST can traverse in a faster speed under multi-data background. The designed BIST circuit has high fault detection coverage and fast test speed, and has good reusability. For the performance test of SRAM, we extend the designed BIST, add all digital PLL and delay chain circuit. The high frequency clock and off-chip tunable options generated by ADPLL are used to provide a multi-frequency test environment for analog users of the chip. The delay circuit and off-chip tunable options are used to measure the access time of SRAM and other performance parameters. In this paper, the principle and testing process of measuring SRAM performance parameters for real speed test chip are described in detail, and the real speed test chip is tested under the test environment of 25 鈩，
本文編號：2424243
[Abstract]:With the decreasing of IC feature size and the increasing of circuit working frequency, the memory fault is no longer a simple functional fault. The performance failure caused by the weak delay of the circuit has also become a problem that must be considered in the design and testing of integrated circuits. Based on memory built-in self-test technology, this paper studies the design and test of SRAM real speed test chip for static random access memory, and proposes a BIST system based on improved algorithm design. The real speed testing system is designed by using the BIST extension, and the principle of memory real speed testing is analyzed. The SRAM IP is tested with the designed real speed test chip. The test object of SRAM real-speed test is the function test and performance test of SRAM IP. For function testing, this paper first analyzes the common fault types of memory, and studies several commonly used memory testing algorithms. On this basis, a test graph generation mechanism combining improved March C algorithm and chessboard test is proposed. The improved algorithm can effectively detect coupling failure and near graph sensitive failure that can not be detected by traditional March C algorithm. Based on the improved algorithm, the built-in self-test circuit is designed with the top-down idea, and the hardware implementation and simulation are given. The simulation results show that the designed BIST can traverse in a faster speed under multi-data background. The designed BIST circuit has high fault detection coverage and fast test speed, and has good reusability. For the performance test of SRAM, we extend the designed BIST, add all digital PLL and delay chain circuit. The high frequency clock and off-chip tunable options generated by ADPLL are used to provide a multi-frequency test environment for analog users of the chip. The delay circuit and off-chip tunable options are used to measure the access time of SRAM and other performance parameters. In this paper, the principle and testing process of measuring SRAM performance parameters for real speed test chip are described in detail, and the real speed test chip is tested under the test environment of 25 鈩，
本文編號：2424243
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