金屬浮柵存儲器的結(jié)構(gòu)優(yōu)化和性能分析
發(fā)布時間：2019-01-18 16:08
【摘要】：Flash存儲器由于其高集成度、低功耗、高可靠性和高性價比等優(yōu)點,在非易失性存儲器市場中占據(jù)了主要的份額。但隨著微電子技術(shù)的發(fā)展,Flash存儲器也面臨了一系列的挑戰(zhàn),如更低的功耗,更快的速度,更高的集成度等。對于傳統(tǒng)多晶硅浮柵存儲器而言,多晶硅浮柵的厚度隨著器件特征尺寸的減小而同步減薄,這使得具有高能量的入射電子增多。大量的高能入射電子對阻擋氧化層造成損傷,產(chǎn)生更多的陷阱和缺陷,影響器件的可靠性。為了克服這一問題,以金屬替代多晶硅作為浮柵的方案被提出來,因此對金屬浮柵存儲器性能的研究和改善得到了比較廣泛的關(guān)注。本論文主要以金屬浮柵存儲器為研究對象,通過對浮柵結(jié)構(gòu)進(jìn)行優(yōu)化,改進(jìn)存儲器編程/擦除性能。金屬浮柵存儲器的浮柵材料的功函數(shù)對器件性能有很大影響,因此本論文首先對浮柵材料的功函數(shù)對器件性能的影響做了研究。在此基礎(chǔ)上通過調(diào)整和優(yōu)化金屬浮柵結(jié)構(gòu),改變溝道內(nèi)電場分布和浮柵耦合電勢,研究了金屬浮柵結(jié)構(gòu)對存儲器性能的影響。結(jié)果表明,對金屬浮柵結(jié)構(gòu)進(jìn)行優(yōu)化后,溝道電場分布出現(xiàn)局部峰值,提升了溝道內(nèi)熱電子的動能,從而促進(jìn)編程過程中電子的注入效率;同時,浮柵中耦合的電勢也得到提升,進(jìn)而增強(qiáng)編程過程中的垂直電場,進(jìn)一步提高熱電子的注入效率。在擦除過程中,由于垂直電場的增強(qiáng),使存儲在金屬浮柵中的電荷更容易通過F-N隧穿回到襯底。通過對比,優(yōu)化后的器件在相同的閾值電壓改變量(編程和擦除過程中分別為3.5V和-3.5V)情況下所需的編程時間縮短了77%,擦除時間縮短了52%,器件的編程/擦除性能得到了提升。SOI技術(shù)對器件性能有很大的影響,因此本論文研究了SOI襯底上的金屬浮柵存儲器的性能,并提出了改進(jìn)方案。模擬結(jié)果表明,SOI頂層硅厚度為5nm時存儲器的編程和擦除性能達(dá)到最優(yōu)。在此基礎(chǔ)上,本論文對在SOI襯底上的金屬浮柵存儲器的浮柵結(jié)構(gòu)也進(jìn)行了優(yōu)化。優(yōu)化后存儲器的存儲窗口提升了32%,并且在相同的閾值電壓改變量(編程和擦除過程中分別為3.5V和-3.5V)情況下所需的編程時間縮短了73%,擦除時間縮短了64%。在此基礎(chǔ)上本論文研究了高k材料作為器件控制柵介質(zhì)層時對器件性能的影響。仿真結(jié)果表明,高k材料作為控制柵介質(zhì)層能進(jìn)一步提升器件的編程/擦除性能。最后,設(shè)計了一種制造優(yōu)化的SOI金屬浮柵存儲器的工藝流程,該工藝與標(biāo)準(zhǔn)硅CMOS技術(shù)相兼容。借助Silvaco TCAD工藝模擬工具,論文中模擬了SOI金屬浮柵存儲器的工藝流程。通過模擬仿真,證實了本文提出的方案的可行性。
[Abstract]:Because of its advantages of high integration, low power consumption, high reliability and high cost performance, Flash memory occupies a major share in the non-volatile memory market. However, with the development of microelectronics technology, Flash memory also faces a series of challenges, such as lower power consumption, faster speed, higher integration and so on. For the conventional polysilicon floating gate memory, the thickness of the polysilicon floating gate decreases synchronously with the decrease of the characteristic size of the device, which makes the incident electrons with high energy increase. A large number of high energy incident electrons damage the oxide barrier and produce more traps and defects which affect the reliability of the device. In order to overcome this problem, the scheme of metal instead of polysilicon as floating gate has been put forward, so the research and improvement of metal floating gate memory have been paid more attention. In this paper, the metal floating gate memory is studied, and the memory programming / erasing performance is improved by optimizing the floating gate structure. The work function of the floating gate material of metal floating gate memory has great influence on the performance of the device, so the influence of the work function of the floating gate material on the performance of the device is studied in this paper. On this basis, the influence of metal floating gate structure on memory performance is studied by adjusting and optimizing the metal floating gate structure, changing the electric field distribution in the channel and the floating gate coupling potential. The results show that after the optimization of the metal floating gate structure, the local peak value of the channel electric field appears, which enhances the kinetic energy of the hot electron in the channel and thus promotes the efficiency of electron injection in the programming process. At the same time, the coupling potential in the floating gate is also enhanced, which enhances the vertical electric field in the programming process and further improves the injection efficiency of hot electrons. During the erasure process the charge stored in the metal floating gate is easier to return to the substrate through the F-N tunneling due to the enhancement of the vertical electric field. By comparison, the optimized device reduces the programming time and erasure time by 7777V and 52V respectively under the same threshold voltage change (3.5V and -3.5V in programming and erasing process, respectively). The programming / erasure performance of the device has been improved. The SOI technology has great influence on the device performance. Therefore, the performance of metal floating gate memory on SOI substrate is studied in this paper, and an improved scheme is proposed. The simulation results show that the memory programming and erasure performance is optimal when the top silicon thickness of SOI is 5nm. On this basis, the floating gate structure of metal floating gate memory on SOI substrate is also optimized. The memory window of the optimized memory is increased by 32 and the programming time and the erasure time are shortened by 73 and 64 respectively in the case of the same threshold voltage change (3.5V and -3.5V in the programming and erasure process respectively). On this basis, the effect of high k material as gate dielectric layer on device performance is studied. The simulation results show that the high k material as the control gate dielectric layer can further improve the programming / erasure performance of the device. Finally, a process of manufacturing optimized SOI metal floating gate memory is designed, which is compatible with standard silicon CMOS technology. With the aid of Silvaco TCAD process simulation tool, the process of SOI metal floating gate memory is simulated in this paper. The feasibility of the proposed scheme is verified by simulation.
【學(xué)位授予單位】：南京郵電大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TP333
[Abstract]:Because of its advantages of high integration, low power consumption, high reliability and high cost performance, Flash memory occupies a major share in the non-volatile memory market. However, with the development of microelectronics technology, Flash memory also faces a series of challenges, such as lower power consumption, faster speed, higher integration and so on. For the conventional polysilicon floating gate memory, the thickness of the polysilicon floating gate decreases synchronously with the decrease of the characteristic size of the device, which makes the incident electrons with high energy increase. A large number of high energy incident electrons damage the oxide barrier and produce more traps and defects which affect the reliability of the device. In order to overcome this problem, the scheme of metal instead of polysilicon as floating gate has been put forward, so the research and improvement of metal floating gate memory have been paid more attention. In this paper, the metal floating gate memory is studied, and the memory programming / erasing performance is improved by optimizing the floating gate structure. The work function of the floating gate material of metal floating gate memory has great influence on the performance of the device, so the influence of the work function of the floating gate material on the performance of the device is studied in this paper. On this basis, the influence of metal floating gate structure on memory performance is studied by adjusting and optimizing the metal floating gate structure, changing the electric field distribution in the channel and the floating gate coupling potential. The results show that after the optimization of the metal floating gate structure, the local peak value of the channel electric field appears, which enhances the kinetic energy of the hot electron in the channel and thus promotes the efficiency of electron injection in the programming process. At the same time, the coupling potential in the floating gate is also enhanced, which enhances the vertical electric field in the programming process and further improves the injection efficiency of hot electrons. During the erasure process the charge stored in the metal floating gate is easier to return to the substrate through the F-N tunneling due to the enhancement of the vertical electric field. By comparison, the optimized device reduces the programming time and erasure time by 7777V and 52V respectively under the same threshold voltage change (3.5V and -3.5V in programming and erasing process, respectively). The programming / erasure performance of the device has been improved. The SOI technology has great influence on the device performance. Therefore, the performance of metal floating gate memory on SOI substrate is studied in this paper, and an improved scheme is proposed. The simulation results show that the memory programming and erasure performance is optimal when the top silicon thickness of SOI is 5nm. On this basis, the floating gate structure of metal floating gate memory on SOI substrate is also optimized. The memory window of the optimized memory is increased by 32 and the programming time and the erasure time are shortened by 73 and 64 respectively in the case of the same threshold voltage change (3.5V and -3.5V in the programming and erasure process respectively). On this basis, the effect of high k material as gate dielectric layer on device performance is studied. The simulation results show that the high k material as the control gate dielectric layer can further improve the programming / erasure performance of the device. Finally, a process of manufacturing optimized SOI metal floating gate memory is designed, which is compatible with standard silicon CMOS technology. With the aid of Silvaco TCAD process simulation tool, the process of SOI metal floating gate memory is simulated in this paper. The feasibility of the proposed scheme is verified by simulation.
【學(xué)位授予單位】：南京郵電大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TP333
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