基于SRAM型FPGA的抗單粒子效應(yīng)容錯(cuò)技術(shù)的研究
發(fā)布時(shí)間：2019-01-12 10:36
【摘要】：SRAM型FPGA具有開發(fā)成本低，高密度等特性，使得其逐步應(yīng)用到航空航天領(lǐng)域，但由于SRAM型FPGA是易失性存儲(chǔ)，很容易受到單粒子效應(yīng)的影響。國外對(duì)FPGA的單粒子效應(yīng)檢測(cè)和加固方面進(jìn)行了大量工作，生成了多種FPGA的測(cè)試報(bào)告。目前，國內(nèi)主要進(jìn)行FPGA的單粒子檢測(cè)，對(duì)FPGA的容錯(cuò)加固的研究還很少。因此，本文通過研究FPGA的基本結(jié)構(gòu)和工作原理，分析研究SRAM型FPGA的單粒子效應(yīng)，特別是SEU對(duì)FPGA的影響。針對(duì)現(xiàn)有的SEU緩解技術(shù)展開了一系列的研究，主要工作與創(chuàng)新如下： 1.由于傳統(tǒng)TMR設(shè)計(jì)的容錯(cuò)系統(tǒng)受制于多數(shù)表決器（Voter），因此，深入研究了Xilinx提出的XTMR方法， XTMR方法可以使在三模冗余中的任何一條路徑發(fā)生SEU時(shí)都能輸出正確的結(jié)果。 2.從TMR和EDAC兩個(gè)方面對(duì)BRAM加固進(jìn)行研究，實(shí)現(xiàn)了用漢明碼對(duì)任意數(shù)據(jù)位寬度的存儲(chǔ)器加固，為了糾正多比特?cái)?shù)據(jù)翻轉(zhuǎn)，提出了用RM(2,5)碼加固BRAM存儲(chǔ)器。另一方面，考慮到EDAC模塊本身不具有抗輻射的能力，提出了對(duì)EDAC模塊進(jìn)行三模冗余加固設(shè)計(jì)。 3.由于Virtex-4器件具有回讀和動(dòng)態(tài)重配置功能，本文深入研究其配置過程，配置原理以及容錯(cuò)設(shè)計(jì)中采用的擦洗、回讀技術(shù)等。 4.根據(jù)現(xiàn)有的容錯(cuò)方法設(shè)計(jì)一些容錯(cuò)功能電路。實(shí)現(xiàn)了移位寄存器和UART的三模冗余設(shè)計(jì)。分別用綜合約束和Hamming-3碼實(shí)現(xiàn)了狀態(tài)機(jī)的抗SEU。結(jié)合EDAC和TMR方法設(shè)計(jì)了容錯(cuò)異步串行收發(fā)器IP核，，并進(jìn)行故障注入仿真，仿真結(jié)果表明達(dá)到設(shè)計(jì)要求。 最后，通過分析單粒子效應(yīng)對(duì)FPGA的影響，針對(duì)實(shí)際工程對(duì)系統(tǒng)可靠性和性能等方面的要求給出了電路設(shè)計(jì)容錯(cuò)加固策略。
[Abstract]:SRAM type FPGA has the characteristics of low development cost and high density, which makes it applied to aerospace field step by step. However, because SRAM type FPGA is volatile storage, it is easy to be affected by single particle effect. A great deal of work has been done in the field of single particle effect detection and reinforcement of FPGA abroad, and a variety of FPGA test reports have been generated. At present, the single particle detection of FPGA is mainly carried out in China, and the research on fault tolerant reinforcement of FPGA is still rare. Therefore, by studying the basic structure and working principle of FPGA, the single particle effect of SRAM type FPGA, especially the influence of SEU on FPGA, is analyzed. A series of research on the existing SEU mitigation technology has been carried out. The main work and innovation are as follows: 1. Because the fault tolerant system designed by traditional TMR is subject to the majority of determinators (Voter), the XTMR method proposed by Xilinx is studied in depth. The XTMR method can output correct results when any path in tri-mode redundancy occurs SEU. 2. The reinforcement of BRAM is studied from two aspects of TMR and EDAC. The hamming code is used to reinforce the memory of any data bit width. In order to correct the multi-bit data flipping, the RM (2P5) code is proposed to reinforce the BRAM memory. On the other hand, considering that the EDAC module itself does not have the ability to resist radiation, a three-mode redundant reinforcement design for the EDAC module is proposed. 3. Because Virtex-4 devices have the functions of backreading and dynamic reconfiguration, the configuration process, configuration principle, scrubbing and rereading techniques used in fault-tolerant design are studied in this paper. 4. Some fault-tolerant function circuits are designed according to the existing fault-tolerant methods. The design of shift register and UART is realized. The anti-SEU. of state machine is realized by synthesizing constraint and Hamming-3 code, respectively. The fault-tolerant asynchronous serial transceiver IP core is designed based on EDAC and TMR method, and the fault injection simulation is carried out. The simulation results show that the design requirements are met. Finally, by analyzing the effect of single particle effect on FPGA, the fault-tolerant reinforcement strategy of circuit design is proposed to meet the requirements of system reliability and performance in practical engineering.
【學(xué)位授予單位】：西北師范大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP333;TN791
本文編號(hào)：2407682
[Abstract]:SRAM type FPGA has the characteristics of low development cost and high density, which makes it applied to aerospace field step by step. However, because SRAM type FPGA is volatile storage, it is easy to be affected by single particle effect. A great deal of work has been done in the field of single particle effect detection and reinforcement of FPGA abroad, and a variety of FPGA test reports have been generated. At present, the single particle detection of FPGA is mainly carried out in China, and the research on fault tolerant reinforcement of FPGA is still rare. Therefore, by studying the basic structure and working principle of FPGA, the single particle effect of SRAM type FPGA, especially the influence of SEU on FPGA, is analyzed. A series of research on the existing SEU mitigation technology has been carried out. The main work and innovation are as follows: 1. Because the fault tolerant system designed by traditional TMR is subject to the majority of determinators (Voter), the XTMR method proposed by Xilinx is studied in depth. The XTMR method can output correct results when any path in tri-mode redundancy occurs SEU. 2. The reinforcement of BRAM is studied from two aspects of TMR and EDAC. The hamming code is used to reinforce the memory of any data bit width. In order to correct the multi-bit data flipping, the RM (2P5) code is proposed to reinforce the BRAM memory. On the other hand, considering that the EDAC module itself does not have the ability to resist radiation, a three-mode redundant reinforcement design for the EDAC module is proposed. 3. Because Virtex-4 devices have the functions of backreading and dynamic reconfiguration, the configuration process, configuration principle, scrubbing and rereading techniques used in fault-tolerant design are studied in this paper. 4. Some fault-tolerant function circuits are designed according to the existing fault-tolerant methods. The design of shift register and UART is realized. The anti-SEU. of state machine is realized by synthesizing constraint and Hamming-3 code, respectively. The fault-tolerant asynchronous serial transceiver IP core is designed based on EDAC and TMR method, and the fault injection simulation is carried out. The simulation results show that the design requirements are met. Finally, by analyzing the effect of single particle effect on FPGA, the fault-tolerant reinforcement strategy of circuit design is proposed to meet the requirements of system reliability and performance in practical engineering.
【學(xué)位授予單位】：西北師范大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP333;TN791
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