【摘要】：H.264是國(guó)際標(biāo)準(zhǔn)化組織（ISO）和國(guó)際電信聯(lián)盟（ITU）共同提出的繼MPEG4之后的新一代數(shù)字視頻壓縮格式。作為H.264解碼器的重要組成單元DDR2存儲(chǔ)器接口，在該項(xiàng)目中的作用是將視頻解碼核產(chǎn)生中間數(shù)據(jù)緩存于片外存儲(chǔ)器（或從外存中讀出），同時(shí)DDR2存儲(chǔ)器接口還提供與視頻解碼核的通信，視頻輸出控制模塊通過(guò)DDR2存儲(chǔ)接口從DDR2SDRAM中讀取數(shù)據(jù)。 本論文在研究了DDR2的JEDEC標(biāo)準(zhǔn)，H.264協(xié)議的基礎(chǔ)上，設(shè)計(jì)出了滿(mǎn)足解碼器需求的DDR2存儲(chǔ)器接口的整體架構(gòu)。根據(jù)H.264解碼核的接口要求對(duì)DDR2存儲(chǔ)器接口進(jìn)行了整體架構(gòu)的設(shè)計(jì)，確定系統(tǒng)所要實(shí)現(xiàn)的功能、系統(tǒng)的輸入輸出以及這些輸入輸出之間的關(guān)系，使其能夠在整個(gè)解碼器中正常良好的運(yùn)行。 DDR2控制器接口由兩大部分組成，分別為控制器接口和DDR2控制器。論文主要完成了整個(gè)控制器接口和DDR2控制器部分模塊的RTL設(shè)計(jì)，并在文章中詳細(xì)介紹了控制器接口的各個(gè)模塊，以及其內(nèi)部組成，，接口信號(hào)，接口時(shí)序。設(shè)計(jì)難點(diǎn)在于數(shù)據(jù)類(lèi)型較多，仲裁情況復(fù)雜，存儲(chǔ)方式的優(yōu)化。在學(xué)習(xí)DDR2規(guī)范的基礎(chǔ)上，研究國(guó)內(nèi)外DDR2控制器的設(shè)計(jì)經(jīng)驗(yàn)，對(duì)DDR2控制器進(jìn)行系統(tǒng)功能分析，設(shè)計(jì)了DDR2控制器中用戶(hù)接口模塊，參數(shù)配置模塊以及控制模塊。并在此基礎(chǔ)上詳細(xì)介紹了phy模塊設(shè)計(jì)方法。設(shè)計(jì)難點(diǎn)在于控制器中狀態(tài)的轉(zhuǎn)換，自刷新等操作時(shí)間的詳細(xì)控制等。 在實(shí)現(xiàn)RTL代碼設(shè)計(jì)的基礎(chǔ)上，作者根據(jù)解碼核發(fā)送的數(shù)據(jù)情況獨(dú)立了搭建驗(yàn)證平臺(tái)，進(jìn)行了驗(yàn)證項(xiàng)的提取，完成了DDR2存儲(chǔ)器接口的功能驗(yàn)證。難點(diǎn)在于解碼核功能模型實(shí)現(xiàn)實(shí)際情況下發(fā)送數(shù)據(jù)，請(qǐng)求等所有的情況的全覆蓋，以確保功能的健全。由于存儲(chǔ)數(shù)據(jù)量大，所以實(shí)現(xiàn)數(shù)據(jù)的自動(dòng)對(duì)比也是其中的難點(diǎn)之一。 論文設(shè)計(jì)的DDR2存儲(chǔ)器接口主要特點(diǎn)是： 1.使用于H.264解碼芯片，可以直接與解碼核相連。 2.對(duì)發(fā)送來(lái)的數(shù)據(jù)請(qǐng)求進(jìn)行了兩級(jí)仲裁，確保請(qǐng)求能夠正常響應(yīng)，數(shù)據(jù)正常傳輸，提高DDR2SDRAM的存儲(chǔ)效率。 3.支持DDR2三項(xiàng)新技術(shù)，充分發(fā)揮DDR2SDRAM的特性。 4.自動(dòng)DDR2刷新控制，方便用戶(hù)對(duì)DDR2刷新的控制。
[Abstract]:H.264 is a new digital video compression format proposed by the International Organization for Standardization (ISO) and the International Telecommunication Union (ITU) after MPEG4. As an important component of the H.264 decoder, the DDR2 memory interface is used in this project to cache the intermediate data generated by the video decoding core (or read out from the external memory). At the same time, the DDR2 memory interface also provides the communication with the video decoding core, and the video output control module reads the data from the DDR2SDRAM through the DDR2 storage interface. Based on the research of JEDEC standard and H.264 protocol of DDR2, this paper designs the whole architecture of DDR2 memory interface which meets the requirements of decoder. According to the interface requirements of H.264 decoding core, the DDR2 memory interface is designed as a whole, and the functions of the system, the input and output of the system and the relationship between these inputs and outputs are determined. Make it work well in the whole decoder. DDR2 controller interface is composed of two parts, controller interface and DDR2 controller. This paper mainly completes the RTL design of the whole controller interface and the DDR2 controller module, and introduces in detail each module of the controller interface, as well as its internal composition, interface signal, interface timing. The difficulty of design is that there are many data types, arbitration is complicated, and storage mode is optimized. Based on the study of DDR2 specification, the design experience of DDR2 controller at home and abroad is studied, and the system function of DDR2 controller is analyzed. The user interface module, parameter configuration module and control module in DDR2 controller are designed. On this basis, the design method of phy module is introduced in detail. The design difficulty lies in the conversion of the state in the controller, the detailed control of the operation time such as self-refresh, etc. Based on the design of RTL code, the author builds an independent verification platform according to the data sent by the decoding core, extracts the verification items, and completes the functional verification of the DDR2 memory interface. The difficulty lies in decoding the kernel function model to realize the full coverage of all the cases such as sending data and requesting data in practice so as to ensure the soundness of the function. Because of the large amount of data stored, automatic data comparison is one of the difficulties. The main features of the DDR2 memory interface designed in this paper are as follows: 1. Used in H. 264 decoding chip, can be directly connected to the decoding core. 2. Two levels of arbitration are carried out to ensure that the request can respond normally, the data can be transmitted normally, and the storage efficiency of DDR2SDRAM can be improved. 3. Support DDR2 three new technologies, give full play to the characteristics of DDR2SDRAM. 4. Automatic DDR2 refresh control, easy for users to DDR2 refresh control.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類(lèi)號(hào)】：TP333;TN919.81

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本文編號(hào)：2399365