【摘要】：在圖像數(shù)據(jù)采集中,存儲(chǔ)體系需要滿足對(duì)圖像數(shù)據(jù)持續(xù)高速存儲(chǔ)的要求。針對(duì)某圖像信息處理器的性能測(cè)試需求,開發(fā)了圖像數(shù)據(jù)的高速并行化存儲(chǔ)體系。為實(shí)現(xiàn)圖像數(shù)據(jù)的大容量、高速、高可靠、低功耗的存儲(chǔ)需求,本文致力于研究一種圖像數(shù)據(jù)高速存儲(chǔ)方法,并對(duì)高速存儲(chǔ)涉及的高可靠低功耗進(jìn)行了深入研究。首先,為了實(shí)現(xiàn)200 MB/s的持續(xù)存儲(chǔ)速度,借鑒流水線和并行擴(kuò)展的思路,設(shè)計(jì)了一種結(jié)構(gòu)為5×8的Flash存儲(chǔ)陣列。以狀態(tài)機(jī)實(shí)現(xiàn)通道內(nèi)和通道間的流水線設(shè)計(jì),通過雙流水線形式的并行工作模式,充分發(fā)揮每一片NAND Flash的存儲(chǔ)性能以實(shí)現(xiàn)圖像數(shù)據(jù)的持續(xù)高速存儲(chǔ)。其次,在可靠性方面,針對(duì)Flash陣列的無效塊管理問題,提出了兩種無效塊管理方案,并分析了兩種無效塊管理方案的優(yōu)缺點(diǎn),選擇了基于組合塊理念的無效塊管理方案;同時(shí),為了解決突發(fā)無效塊對(duì)高速存儲(chǔ)的影響,設(shè)計(jì)了滯后重寫機(jī)制。另外,針對(duì)Flash芯片單比特翻轉(zhuǎn)造成的數(shù)據(jù)誤碼,提出了雙緩存交替的漢明碼糾錯(cuò)方案,該方案在不影響數(shù)據(jù)讀取速度的情況下,有效避免了Flash的單比特誤碼的產(chǎn)生。最后,為了降低FPGA功耗,減少芯片發(fā)熱,提出了一種程序低功耗優(yōu)化方法,采用這種設(shè)計(jì)方法可以大幅減小內(nèi)部的邏輯資源、布線資源的使用,從而達(dá)到降低動(dòng)態(tài)功耗,提高FPGA程序運(yùn)行可靠性的目的。通過對(duì)各項(xiàng)技術(shù)指標(biāo)以及系統(tǒng)總體的性能進(jìn)行測(cè)試,并分析得到的測(cè)試數(shù)據(jù),設(shè)計(jì)的Flash陣列可以達(dá)到200MB/s的數(shù)據(jù)存儲(chǔ)速率。通過大量試驗(yàn)證明,存儲(chǔ)體系的存儲(chǔ)速率以及容量均滿足設(shè)計(jì)指標(biāo),工作穩(wěn)定可靠。
[Abstract]:In image data acquisition, the storage system needs to meet the requirements of image data storage. A high speed parallel storage system for image data is developed to meet the performance test requirements of an image information processor. In order to realize the storage requirements of large capacity, high speed, high reliability and low power consumption of image data, this paper focuses on a high speed storage method of image data, and deeply studies the high reliability and low power consumption involved in high speed storage. Firstly, in order to realize the continuous storage speed of 200 MB/s, a 5 脳 8 Flash memory array is designed based on the idea of pipeline and parallel expansion. The state machine is used to design pipeline in and between channels, and the storage performance of each piece of NAND Flash is brought into full play through the parallel working mode in the form of dual pipeline to realize the continuous high speed storage of image data. Secondly, in the aspect of reliability, aiming at the invalid block management of Flash array, two invalid block management schemes are proposed, and the advantages and disadvantages of two invalid block management schemes are analyzed, and the invalid block management scheme based on composite block concept is selected. At the same time, in order to solve the impact of burst invalid block on high speed storage, a delay rewriting mechanism is designed. In addition, aiming at the data error caused by single bit flipping in Flash chip, a double buffer alternating hamming code correction scheme is proposed, which can effectively avoid the generation of single bit error code of Flash without affecting the data reading speed. Finally, in order to reduce FPGA power consumption and chip heating, a program low-power optimization method is proposed, which can greatly reduce the use of internal logic resources and wiring resources, thereby reducing the dynamic power consumption. The purpose of improving the reliability of FPGA program. By testing the technical specifications and the overall performance of the system, and analyzing the test data, the designed Flash array can achieve the data storage rate of 200MB/s. Through a lot of experiments, it is proved that the storage rate and capacity of the storage system meet the design index and work stably and reliably.
【學(xué)位授予單位】：中北大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TP333;TP391.41

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