基于交點隊列型Crossbar的多層AXI總線設計
發(fā)布時間：2018-12-10 12:07
【摘要】：AXI總線內(nèi)部傳統(tǒng)的核間通信結構對處理器核之間的通信存在多方面的限制,已難以滿足多核SoC(System on Chip)日益發(fā)展的性能需求。提出以交點隊列(Crosspiont-Queued,CQ)型Crossbar代替?zhèn)鹘y(tǒng)的核間通信結構,設計一種多層AXI總線。通過Simulink工具對交點隊列型核間通信結構進行建模與仿真,確定其交點緩存的最佳深度。并結合VCS仿真工具對所設計的RTL代碼進行了全方面的仿真,結果表明,所設計的通信架構能夠完整地實現(xiàn)讀寫功能。
[Abstract]:The traditional inter-core communication architecture in AXI bus has many limitations on the communication between processor cores, which makes it difficult to meet the growing performance requirements of multi-core SoC (System on Chip). In this paper, a multi-layer AXI bus is designed by replacing the traditional inter-core communication structure with the intersection queue (Crosspiont-Queued,CQ) type Crossbar. The intercore communication structure of intersection queue type is modeled and simulated by Simulink tool, and the optimum depth of intersecting buffer is determined. Combined with the VCS simulation tool, the designed RTL code is simulated in all aspects. The results show that the designed communication architecture can complete the function of reading and writing.
【作者單位】： 蘇州大學電子信息學院;中國兵器工業(yè)集團北方電子研究院有限公司微電子部;
【分類號】：TP336
本文編號：2370541
[Abstract]:The traditional inter-core communication architecture in AXI bus has many limitations on the communication between processor cores, which makes it difficult to meet the growing performance requirements of multi-core SoC (System on Chip). In this paper, a multi-layer AXI bus is designed by replacing the traditional inter-core communication structure with the intersection queue (Crosspiont-Queued,CQ) type Crossbar. The intercore communication structure of intersection queue type is modeled and simulated by Simulink tool, and the optimum depth of intersecting buffer is determined. Combined with the VCS simulation tool, the designed RTL code is simulated in all aspects. The results show that the designed communication architecture can complete the function of reading and writing.
【作者單位】： 蘇州大學電子信息學院;中國兵器工業(yè)集團北方電子研究院有限公司微電子部;
【分類號】：TP336
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1 林曉牧;基于AXI接口的多模式AES加解密IP核設計與實現(xiàn)[D];華南理工大學;2010年
2 胡景華;基于AXI總線的SoC架構設計與分析[D];上海交通大學;2013年
3 季順南;基于AXI總線的DMA控制器的研究與設計[D];華南理工大學;2010年
4 任慈軍;基于AXI總線的DDR數(shù)據(jù)流量監(jiān)控器的設計[D];安徽大學;2015年
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