基于FPGA的高速實(shí)時(shí)數(shù)據(jù)采集存儲(chǔ)系統(tǒng)的設(shè)計(jì)
發(fā)布時(shí)間：2018-11-28 07:49
【摘要】：隨著現(xiàn)代科技高速發(fā)展,在工業(yè)生產(chǎn)和科學(xué)研究上如無線通信、圖像處理、核磁共振波譜儀等領(lǐng)域,都需要在各級(jí)設(shè)備間高速傳輸大量的數(shù)據(jù)。因此需要在系統(tǒng)設(shè)計(jì)中運(yùn)用大容量、高速的存儲(chǔ)介質(zhì)。隨著科技進(jìn)的步,人們開始使用內(nèi)存,內(nèi)存產(chǎn)品也正在不斷演進(jìn),從最初的DRAM一直發(fā)展到今天在本論文中使用到的DDR3SDRAM。在時(shí)序控制方面,FPGA芯片具有較高的時(shí)鐘頻率和豐富的硬件資源,能夠快速有效的控制復(fù)雜的組合邏輯和時(shí)序邏輯電路。所以通過將FPGA和DDR3SDRAM相結(jié)合的接口時(shí)序設(shè)計(jì),可以在大容量與高速率的采集存儲(chǔ)系統(tǒng)中起到核心控制作用。 基于該背景,在深入閱讀和理解了FPGA開發(fā)流程和DDR3SDRAM的控制原理、存儲(chǔ)結(jié)構(gòu)、接口時(shí)序等知識(shí)后,本文提出了基于Xilinx公司的Spartan6FPGA作為控制核心,Micron公司的DDR3SDRAM作為存儲(chǔ)介質(zhì),并通過USB2.0系統(tǒng)進(jìn)行數(shù)據(jù)傳輸?shù)母咚俨杉c存儲(chǔ)系統(tǒng),以滿足現(xiàn)代工業(yè)與科學(xué)研究中高速、高實(shí)時(shí)性的數(shù)據(jù)采集存儲(chǔ)要求。 本論文首先介紹了高速采集存儲(chǔ)系統(tǒng)的技術(shù)背景和國內(nèi)外發(fā)展?fàn)顩r,并針對(duì)現(xiàn)有使用DDR或者DDR2內(nèi)存的該系統(tǒng),提出使用DDR3內(nèi)存能更快速讀寫數(shù)據(jù)并具有更大存儲(chǔ)容量的方案。其次,給出了搭建本系統(tǒng)的總體架構(gòu)和論文設(shè)計(jì)的思路,即如何實(shí)現(xiàn)基于FPGA控制的DDR3控制器,并確立了控制器系統(tǒng)中各個(gè)模塊的組成。然后通過ISE12.4開發(fā)平臺(tái)和Verilog HDL的設(shè)計(jì)輸入方式,并結(jié)合了開放的IP核資源,對(duì)每個(gè)模塊進(jìn)行了詳細(xì)的邏輯分析與設(shè)計(jì)。最后運(yùn)用硬件環(huán)境對(duì)所設(shè)計(jì)的系統(tǒng)進(jìn)行測(cè)試,分析了系統(tǒng)資源耗用情況,系統(tǒng)實(shí)時(shí)性和使用chipscope邏輯分析儀工具對(duì)該系統(tǒng)進(jìn)行了功能驗(yàn)證。 驗(yàn)證結(jié)果說明,基于FPGA與DDR3的高速采集存儲(chǔ)系統(tǒng),數(shù)據(jù)吞吐量與讀寫速率較現(xiàn)有系統(tǒng)有很大的提升,達(dá)到了最初系統(tǒng)設(shè)計(jì)的要求。在長時(shí)間不斷電工作下穩(wěn)定運(yùn)行,沒有誤碼的產(chǎn)生。
[Abstract]:With the rapid development of modern science and technology, in industrial production and scientific research, such as wireless communication, image processing, nuclear magnetic resonance spectrometer and other fields, it is necessary to transfer a large amount of data at high speed between various devices. Therefore, it is necessary to use large capacity and high speed storage media in the system design. With the advance of technology, people begin to use memory, and memory products are evolving, from the beginning of DRAM to the DDR3SDRAM. used in this paper. In the aspect of timing control, FPGA chip has high clock frequency and abundant hardware resources, and can control complex combinatorial logic and sequential logic circuits quickly and effectively. Therefore, by combining FPGA and DDR3SDRAM interface timing design, it can play a central control role in large capacity and high speed acquisition and storage system. Based on this background, after deeply reading and understanding the FPGA development process and the knowledge of DDR3SDRAM control principle, storage structure, interface timing and so on, this paper proposes Spartan6FPGA based on Xilinx as the control core and DDR3SDRAM of Micron as the storage medium. In order to meet the requirement of high-speed and real-time data acquisition and storage in modern industrial and scientific research, a high-speed data acquisition and storage system is implemented through USB2.0 system. This paper first introduces the technical background of high-speed acquisition and storage system and the development situation at home and abroad. Aiming at the existing system which uses DDR or DDR2 memory, this paper puts forward a scheme of using DDR3 memory to read and write data more quickly and have more storage capacity. Secondly, the overall architecture of the system and the design idea of the paper are given, that is, how to realize the DDR3 controller based on FPGA control, and the composition of each module in the controller system is established. Then through the ISE12.4 development platform and Verilog HDL design input mode, and combined with the open IP core resources, each module is analyzed and designed in detail. Finally, the system is tested by hardware environment, the system resource consumption is analyzed, the real-time performance of the system is analyzed, and the function of the system is verified by using the chipscope logic analyzer tool. The verification results show that the data throughput and read / write rate of the high speed acquisition and storage system based on FPGA and DDR3 are greatly improved than the existing system, and meet the requirements of the original system design. In a long time without power off under the stable operation, there is no error code generation.
【學(xué)位授予單位】：武漢理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP274.2;TP333
本文編號(hào)：2362263
[Abstract]:With the rapid development of modern science and technology, in industrial production and scientific research, such as wireless communication, image processing, nuclear magnetic resonance spectrometer and other fields, it is necessary to transfer a large amount of data at high speed between various devices. Therefore, it is necessary to use large capacity and high speed storage media in the system design. With the advance of technology, people begin to use memory, and memory products are evolving, from the beginning of DRAM to the DDR3SDRAM. used in this paper. In the aspect of timing control, FPGA chip has high clock frequency and abundant hardware resources, and can control complex combinatorial logic and sequential logic circuits quickly and effectively. Therefore, by combining FPGA and DDR3SDRAM interface timing design, it can play a central control role in large capacity and high speed acquisition and storage system. Based on this background, after deeply reading and understanding the FPGA development process and the knowledge of DDR3SDRAM control principle, storage structure, interface timing and so on, this paper proposes Spartan6FPGA based on Xilinx as the control core and DDR3SDRAM of Micron as the storage medium. In order to meet the requirement of high-speed and real-time data acquisition and storage in modern industrial and scientific research, a high-speed data acquisition and storage system is implemented through USB2.0 system. This paper first introduces the technical background of high-speed acquisition and storage system and the development situation at home and abroad. Aiming at the existing system which uses DDR or DDR2 memory, this paper puts forward a scheme of using DDR3 memory to read and write data more quickly and have more storage capacity. Secondly, the overall architecture of the system and the design idea of the paper are given, that is, how to realize the DDR3 controller based on FPGA control, and the composition of each module in the controller system is established. Then through the ISE12.4 development platform and Verilog HDL design input mode, and combined with the open IP core resources, each module is analyzed and designed in detail. Finally, the system is tested by hardware environment, the system resource consumption is analyzed, the real-time performance of the system is analyzed, and the function of the system is verified by using the chipscope logic analyzer tool. The verification results show that the data throughput and read / write rate of the high speed acquisition and storage system based on FPGA and DDR3 are greatly improved than the existing system, and meet the requirements of the original system design. In a long time without power off under the stable operation, there is no error code generation.
【學(xué)位授予單位】：武漢理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP274.2;TP333
【引證文獻(xiàn)】
相關(guān)碩士學(xué)位論文 前2條
1 劉立;基于MPSoC的DDR3存儲(chǔ)器接口設(shè)計(jì)[D];南京大學(xué);2013年
2 郭浩;基于FPGA的運(yùn)動(dòng)目標(biāo)檢測(cè)系統(tǒng)的設(shè)計(jì)與實(shí)現(xiàn)[D];武漢理工大學(xué);2013年
，本文編號(hào)：2362263
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