70nm分離柵工藝快閃存儲(chǔ)器擦寫性能的改進(jìn)
發(fā)布時(shí)間：2018-11-26 09:53
【摘要】：隨著電子產(chǎn)品的普及,閃存作為當(dāng)今主流的存儲(chǔ)載體得到迅速地推廣,其技術(shù)也得到迅猛地發(fā)展。分離柵快閃存儲(chǔ)器,作為閃存的一種,由于具有高效的編程速度以及完全避免過(guò)擦除的能力,無(wú)論是在單體還是嵌入式產(chǎn)品方面都得到了人們更多的關(guān)注。目前,分離柵快閃存儲(chǔ)器已被廣泛地應(yīng)用于個(gè)人電腦、數(shù)碼器材、移動(dòng)終端、智能卡等產(chǎn)品。 本文首先介紹了分離柵快閃存儲(chǔ)器的工作原理及70nm分離柵工藝快閃存儲(chǔ)器的實(shí)現(xiàn)方法。該分離柵結(jié)構(gòu)的快閃存儲(chǔ)器,采用源端溝道熱電子注入(Source-Side Hot Electron injection)機(jī)制進(jìn)行編程操作,采用浮柵和擦除柵兩層多晶硅間電場(chǎng)增強(qiáng)型隧穿(Poly-to-Poly Enhance Tunneling)進(jìn)行擦除操作,具有著良好的可靠性能和數(shù)據(jù)保持能力。 隨著閃存市場(chǎng)高集成度的發(fā)展需求,分離柵快閃存儲(chǔ)器的尺寸也在逐漸地縮小。在這一縮微過(guò)程中其面臨著擦除效率低下和編程存在干擾的問(wèn)題。在擦除過(guò)程中,由于在70nmm節(jié)點(diǎn)分離柵閃存中不再特意采用浮柵尖角(tip),沒(méi)有足夠的浮柵到擦除柵的正向隧穿電壓,浮柵中部分電子容易被其和擦除柵間的隧穿氧化膜介質(zhì)俘獲,從而無(wú)法徹底擦除。在編程過(guò)程中,雖然其分離柵結(jié)構(gòu)有高效的編程機(jī)制,但是未被編程的單元由于與正在被編程的單元共享位線或者字線,受所加電壓的影響而被編程。原因是分離柵溝道帶帶隧穿效應(yīng)產(chǎn)成的電子-空穴對(duì),在浮柵氧化層發(fā)生隧穿并導(dǎo)致浮柵閾值電壓減小,發(fā)生了編程干擾現(xiàn)象。本文通過(guò)大量實(shí)驗(yàn),從結(jié)構(gòu)和工藝優(yōu)化方面探討對(duì)于分離柵快閃存儲(chǔ)器如何提高它的擦除效率(通過(guò)降低浮柵初始閾值電壓,改變浮柵到擦除柵側(cè)的結(jié)構(gòu)形貌等)和降低它的編程干擾(整合優(yōu)化存儲(chǔ)單元離子注入工藝),進(jìn)而改進(jìn)了70nm分離柵工藝快閃存儲(chǔ)器的擦寫性能。 本論文的研究課題來(lái)源于企業(yè)的研發(fā)實(shí)踐,因此對(duì)于同類型的閃存產(chǎn)品開(kāi)發(fā)和生產(chǎn)制造具有一定的參考意義。
[Abstract]:With the popularity of electronic products flash memory as the mainstream storage carrier has been rapidly popularized and its technology has been rapidly developed. As a kind of flash memory, separation gate flash memory has attracted more and more attention in both single and embedded products due to its high programming speed and the ability to avoid over erasure completely. At present, the separation gate flash memory has been widely used in personal computers, digital devices, mobile terminals, smart cards and other products. This paper first introduces the working principle of the separating gate flash memory and the realization method of the 70nm separation gate technology flash memory. The flash memory with the separation gate structure is programmed by the source end channel hot electron injection (Source-Side Hot Electron injection) mechanism. The electric-field enhanced tunneling (Poly-to-Poly Enhance Tunneling) with floating gate and erasure gate has good reliability and data retention. With the development of high integration in flash memory market, the size of separating gate flash memory is gradually shrinking. In this process, it is faced with the problems of low erasure efficiency and programming interference. In the process of erasing, the forward tunneling voltage from floating gate to erasure gate is not enough because the floating gate angle (tip), is not specially used in the 70nmm node separation gate flash memory. Some electrons in the floating gate are easily captured by the tunneling oxide film medium between them and the erasure gate, so they can not be completely erased. In the process of programming, although the separated gate structure has an efficient programming mechanism, the unprogrammed units are programmed because they share bit lines or word lines with the units being programmed, and are affected by the applied voltage. The reason is that the electron-hole pair produced by the tunneling effect of the separated gate channel band leads to tunneling in the floating gate oxide layer which results in the decrease of the threshold voltage of the floating gate and the programming interference occurs. Through a large number of experiments, this paper discusses how to improve the erasure efficiency of the separation gate flash memory from the aspects of structure and process optimization (by reducing the initial threshold voltage of the floating gate. By changing the structure morphology of the floating gate to erasing the gate side and reducing its programming interference (integrating the optimized memory cell ion implantation process), the erasure performance of the flash memory in the 70nm separation gate process is improved. The research topic of this paper comes from the enterprise's R & D practice, so it has certain reference significance for the development and manufacture of the same type flash memory products.
【學(xué)位授予單位】：復(fù)旦大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP333
本文編號(hào)：2358211
[Abstract]:With the popularity of electronic products flash memory as the mainstream storage carrier has been rapidly popularized and its technology has been rapidly developed. As a kind of flash memory, separation gate flash memory has attracted more and more attention in both single and embedded products due to its high programming speed and the ability to avoid over erasure completely. At present, the separation gate flash memory has been widely used in personal computers, digital devices, mobile terminals, smart cards and other products. This paper first introduces the working principle of the separating gate flash memory and the realization method of the 70nm separation gate technology flash memory. The flash memory with the separation gate structure is programmed by the source end channel hot electron injection (Source-Side Hot Electron injection) mechanism. The electric-field enhanced tunneling (Poly-to-Poly Enhance Tunneling) with floating gate and erasure gate has good reliability and data retention. With the development of high integration in flash memory market, the size of separating gate flash memory is gradually shrinking. In this process, it is faced with the problems of low erasure efficiency and programming interference. In the process of erasing, the forward tunneling voltage from floating gate to erasure gate is not enough because the floating gate angle (tip), is not specially used in the 70nmm node separation gate flash memory. Some electrons in the floating gate are easily captured by the tunneling oxide film medium between them and the erasure gate, so they can not be completely erased. In the process of programming, although the separated gate structure has an efficient programming mechanism, the unprogrammed units are programmed because they share bit lines or word lines with the units being programmed, and are affected by the applied voltage. The reason is that the electron-hole pair produced by the tunneling effect of the separated gate channel band leads to tunneling in the floating gate oxide layer which results in the decrease of the threshold voltage of the floating gate and the programming interference occurs. Through a large number of experiments, this paper discusses how to improve the erasure efficiency of the separation gate flash memory from the aspects of structure and process optimization (by reducing the initial threshold voltage of the floating gate. By changing the structure morphology of the floating gate to erasing the gate side and reducing its programming interference (integrating the optimized memory cell ion implantation process), the erasure performance of the flash memory in the 70nm separation gate process is improved. The research topic of this paper comes from the enterprise's R & D practice, so it has certain reference significance for the development and manufacture of the same type flash memory products.
【學(xué)位授予單位】：復(fù)旦大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP333
【共引文獻(xiàn)】
相關(guān)期刊論文 前2條
1 孟慶龍;張永;;單片機(jī)應(yīng)用中幾個(gè)問(wèn)題的解決方法[J];信息技術(shù)與信息化;2010年03期
2 劉智朋;羅洪元;陽(yáng)小珊;邱全偉;鄭良;;閃存循環(huán)位圖的損耗均衡機(jī)制研究[J];計(jì)算機(jī)工程與設(shè)計(jì);2013年02期
，本文編號(hào)：2358211
本文鏈接：http://sikaile.net/kejilunwen/jisuanjikexuelunwen/2358211.html
最近更新
教材專著
