【摘要】：網(wǎng)絡(luò)用戶(hù)和數(shù)據(jù)流量的指數(shù)級(jí)增長(zhǎng)，要求網(wǎng)絡(luò)處理的帶寬更寬、速度更快。網(wǎng)絡(luò)處理器作為一種基于可編程的ASIC處理器，它可為系統(tǒng)提供類(lèi)似ASIC的高性能處理速度，而且可以提供類(lèi)似通用處理器的靈活性。因此滿足很多應(yīng)用的性能要求。 作為網(wǎng)絡(luò)處理器中的核心設(shè)計(jì)單元，多線程流水線處理器的任務(wù)就是完成對(duì)所有經(jīng)過(guò)網(wǎng)絡(luò)處理器的數(shù)據(jù)包校驗(yàn)和驗(yàn)證，包頭處理和分類(lèi)，，表查找和轉(zhuǎn)發(fā)，包在存儲(chǔ)單元的存儲(chǔ)，包頭修改，包往正確端口的轉(zhuǎn)發(fā)等。因此，多線程流水線處理器設(shè)計(jì)的好壞很大程度上決定了網(wǎng)絡(luò)處理器的性能，多線程流水線處理器的頻率高低直接影響整個(gè)設(shè)計(jì)平臺(tái)的工作頻率，吞吐量以及整體性能。 本文主要完成多線程流水線處理器的設(shè)計(jì)優(yōu)化以及實(shí)現(xiàn)工作：首先對(duì)多線程流水線處理器的指令集以及五級(jí)流水線設(shè)計(jì)和結(jié)構(gòu)進(jìn)行了詳細(xì)分析。多線程流水線處理器主要針對(duì)網(wǎng)絡(luò)數(shù)據(jù)包的處理，相較于一般指令集，多線程流水線處理器指令集對(duì)其中一些指令進(jìn)行了增減；針對(duì)多線程流水線處理器在設(shè)計(jì)時(shí)的流水線沖突問(wèn)題，對(duì)于數(shù)據(jù)沖突和控制沖突分別進(jìn)行了分析并給出了解決方案。其次，在完成基于SMIC0.13μm工藝的ASIC實(shí)現(xiàn)過(guò)程中，首先分析了從FPGA到ASIC設(shè)計(jì)的轉(zhuǎn)換過(guò)程中遇到的問(wèn)題及解決方案。其次，從綜合約束、綜合器優(yōu)化，設(shè)計(jì)優(yōu)化等方面論述了XDNP多線程流水線處理器及仲裁的綜合和優(yōu)化過(guò)程，重點(diǎn)說(shuō)明了綜合的時(shí)序違例和優(yōu)化采取的方法。經(jīng)過(guò)優(yōu)化后的多線程流水線處理器最高工作頻率達(dá)到300MHz，超過(guò)系統(tǒng)設(shè)計(jì)目標(biāo)頻率要求，并且完成了對(duì)多線程流水線處理器的綜合后驗(yàn)證工作。最后根據(jù)綜合得到的網(wǎng)表和約束文件參與完成了多線程流水線處理器的物理設(shè)計(jì)布局布線工作。
[Abstract]:The exponential growth of network users and data traffic requires wider bandwidth and faster processing speed. As a programmable ASIC processor, network processor can provide high performance processing speed similar to ASIC, and provide flexibility similar to general processor. Therefore, it meets the performance requirements of many applications. As the core design unit of network processor, the task of multithreading pipeline processor is to complete the verification of all packets through network processor, packet header processing and classification, table lookup and forwarding, and storage of packets in storage unit. Packet head modification, packet forwarding to the correct port, etc. Therefore, the performance of network processors is largely determined by the design of multithreaded pipelined processors. The frequency of multithreaded pipelined processors directly affects the working frequency, throughput and overall performance of the whole design platform. This paper mainly completes the design optimization and implementation of multithreaded pipeline processor. Firstly, the instruction set and five-stage pipeline design and structure of multithreaded pipeline processor are analyzed in detail. Multi-thread pipelined processor is mainly aimed at the processing of network data packet. Compared with general instruction set, multi-thread pipeline processor instruction set adds and subtracts some of the instructions. Aiming at the problem of pipeline conflict in the design of multithreaded pipelined processor, the data conflict and control conflict are analyzed and the solutions are given. Secondly, in the process of ASIC implementation based on SMIC0.13 渭 m process, the problems and solutions in the conversion process from FPGA to ASIC are analyzed. Secondly, the synthesis and optimization process of XDNP multithreaded pipeline processor and arbitration are discussed from the aspects of synthesis constraint, synthesizer optimization and design optimization. The optimized multithreaded pipelined processor has the highest working frequency of 300MHz, which exceeds the target frequency requirement of the system design, and the synthesis and verification of the multithreaded pipelined processor is completed. Finally, the physical layout and routing of multithreaded pipeline processor is completed according to the network table and constraint file.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類(lèi)號(hào)】：TP332;TN47

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相關(guān)期刊論文 前1條

1 孟李林;;FPGA和ASIC設(shè)計(jì)特點(diǎn)及應(yīng)用探討[J];半導(dǎo)體技術(shù);2006年07期

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