基于IP包處理的多線程流水線處理器ASIC設計與實現(xiàn)
發(fā)布時間：2018-11-24 12:03
【摘要】：網(wǎng)絡用戶和數(shù)據(jù)流量的指數(shù)級增長，要求網(wǎng)絡處理的帶寬更寬、速度更快。網(wǎng)絡處理器作為一種基于可編程的ASIC處理器，它可為系統(tǒng)提供類似ASIC的高性能處理速度，而且可以提供類似通用處理器的靈活性。因此滿足很多應用的性能要求。 作為網(wǎng)絡處理器中的核心設計單元，多線程流水線處理器的任務就是完成對所有經(jīng)過網(wǎng)絡處理器的數(shù)據(jù)包校驗和驗證，包頭處理和分類，，表查找和轉發(fā)，包在存儲單元的存儲，包頭修改，包往正確端口的轉發(fā)等。因此，多線程流水線處理器設計的好壞很大程度上決定了網(wǎng)絡處理器的性能，多線程流水線處理器的頻率高低直接影響整個設計平臺的工作頻率，吞吐量以及整體性能。 本文主要完成多線程流水線處理器的設計優(yōu)化以及實現(xiàn)工作：首先對多線程流水線處理器的指令集以及五級流水線設計和結構進行了詳細分析。多線程流水線處理器主要針對網(wǎng)絡數(shù)據(jù)包的處理，相較于一般指令集，多線程流水線處理器指令集對其中一些指令進行了增減；針對多線程流水線處理器在設計時的流水線沖突問題，對于數(shù)據(jù)沖突和控制沖突分別進行了分析并給出了解決方案。其次，在完成基于SMIC0.13μm工藝的ASIC實現(xiàn)過程中，首先分析了從FPGA到ASIC設計的轉換過程中遇到的問題及解決方案。其次，從綜合約束、綜合器優(yōu)化，設計優(yōu)化等方面論述了XDNP多線程流水線處理器及仲裁的綜合和優(yōu)化過程，重點說明了綜合的時序違例和優(yōu)化采取的方法。經(jīng)過優(yōu)化后的多線程流水線處理器最高工作頻率達到300MHz，超過系統(tǒng)設計目標頻率要求，并且完成了對多線程流水線處理器的綜合后驗證工作。最后根據(jù)綜合得到的網(wǎng)表和約束文件參與完成了多線程流水線處理器的物理設計布局布線工作。
[Abstract]:The exponential growth of network users and data traffic requires wider bandwidth and faster processing speed. As a programmable ASIC processor, network processor can provide high performance processing speed similar to ASIC, and provide flexibility similar to general processor. Therefore, it meets the performance requirements of many applications. As the core design unit of network processor, the task of multithreading pipeline processor is to complete the verification of all packets through network processor, packet header processing and classification, table lookup and forwarding, and storage of packets in storage unit. Packet head modification, packet forwarding to the correct port, etc. Therefore, the performance of network processors is largely determined by the design of multithreaded pipelined processors. The frequency of multithreaded pipelined processors directly affects the working frequency, throughput and overall performance of the whole design platform. This paper mainly completes the design optimization and implementation of multithreaded pipeline processor. Firstly, the instruction set and five-stage pipeline design and structure of multithreaded pipeline processor are analyzed in detail. Multi-thread pipelined processor is mainly aimed at the processing of network data packet. Compared with general instruction set, multi-thread pipeline processor instruction set adds and subtracts some of the instructions. Aiming at the problem of pipeline conflict in the design of multithreaded pipelined processor, the data conflict and control conflict are analyzed and the solutions are given. Secondly, in the process of ASIC implementation based on SMIC0.13 渭 m process, the problems and solutions in the conversion process from FPGA to ASIC are analyzed. Secondly, the synthesis and optimization process of XDNP multithreaded pipeline processor and arbitration are discussed from the aspects of synthesis constraint, synthesizer optimization and design optimization. The optimized multithreaded pipelined processor has the highest working frequency of 300MHz, which exceeds the target frequency requirement of the system design, and the synthesis and verification of the multithreaded pipelined processor is completed. Finally, the physical layout and routing of multithreaded pipeline processor is completed according to the network table and constraint file.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2012
【分類號】：TP332;TN47
本文編號：2353638
[Abstract]:The exponential growth of network users and data traffic requires wider bandwidth and faster processing speed. As a programmable ASIC processor, network processor can provide high performance processing speed similar to ASIC, and provide flexibility similar to general processor. Therefore, it meets the performance requirements of many applications. As the core design unit of network processor, the task of multithreading pipeline processor is to complete the verification of all packets through network processor, packet header processing and classification, table lookup and forwarding, and storage of packets in storage unit. Packet head modification, packet forwarding to the correct port, etc. Therefore, the performance of network processors is largely determined by the design of multithreaded pipelined processors. The frequency of multithreaded pipelined processors directly affects the working frequency, throughput and overall performance of the whole design platform. This paper mainly completes the design optimization and implementation of multithreaded pipeline processor. Firstly, the instruction set and five-stage pipeline design and structure of multithreaded pipeline processor are analyzed in detail. Multi-thread pipelined processor is mainly aimed at the processing of network data packet. Compared with general instruction set, multi-thread pipeline processor instruction set adds and subtracts some of the instructions. Aiming at the problem of pipeline conflict in the design of multithreaded pipelined processor, the data conflict and control conflict are analyzed and the solutions are given. Secondly, in the process of ASIC implementation based on SMIC0.13 渭 m process, the problems and solutions in the conversion process from FPGA to ASIC are analyzed. Secondly, the synthesis and optimization process of XDNP multithreaded pipeline processor and arbitration are discussed from the aspects of synthesis constraint, synthesizer optimization and design optimization. The optimized multithreaded pipelined processor has the highest working frequency of 300MHz, which exceeds the target frequency requirement of the system design, and the synthesis and verification of the multithreaded pipelined processor is completed. Finally, the physical layout and routing of multithreaded pipeline processor is completed according to the network table and constraint file.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2012
【分類號】：TP332;TN47
【參考文獻】
相關期刊論文 前1條
1 孟李林;;FPGA和ASIC設計特點及應用探討[J];半導體技術;2006年07期
本文編號：2353638
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