抗多節(jié)點(diǎn)翻轉(zhuǎn)的存儲器設(shè)計
發(fā)布時間：2018-11-23 15:57
【摘要】：隨著集成電路的迅猛發(fā)展，制造工藝尺寸進(jìn)入了納米級，使得集成電路系統(tǒng)越來越容易受到來自地面環(huán)境和太空環(huán)境中輻射效應(yīng)特別是單粒子翻轉(zhuǎn)（SEU）的影響。而靜態(tài)隨機(jī)存儲器（SRAM）因其速度快、功耗低等優(yōu)良性能也隨著工業(yè)的發(fā)展而占據(jù)越來越重要的位置，，然而它也是集成電路系統(tǒng)中對SEU最為敏感的部分，因此業(yè)界也一直在尋找行之有效的SRAM抗輻射加固技術(shù)。 本文首先研究分析了SRAM工藝級加固、版圖級加固、系統(tǒng)級加固和電路級加固方案以及各個抗SEU加固存儲單元工作機(jī)理�；谀壳凹{米工藝尺寸下這些加固存儲單元鮮有抗多節(jié)點(diǎn)翻轉(zhuǎn)能力，本文最終采用改進(jìn)的DICE單元即TDICE單元設(shè)計了具有抗多節(jié)點(diǎn)翻轉(zhuǎn)能力的容量為128x8bit的SRAM。本文詳細(xì)研究了TDICE單元的性能及SMIC65nm標(biāo)準(zhǔn)單元庫的建庫流程，將TDICE按照標(biāo)單元庫的設(shè)計要求設(shè)計為標(biāo)準(zhǔn)庫單元，并通過了驗(yàn)證使其能夠被EDA工具識別。其次詳細(xì)介紹了SRAM外圍電路的設(shè)計，并進(jìn)行了各電路的功能仿真驗(yàn)證，然后將各部分電路與存儲陣列搭建SRAM整體電路。外圍電路主要包括行列譯碼電路、靈敏放大電路、寫控制電路及數(shù)據(jù)輸入輸出電路等。仿真結(jié)果證明SRAM功能正確。 最后基于SMIC65nm工藝，設(shè)計實(shí)現(xiàn)了各個電路模塊及SRAM整體電路的版圖和后仿真驗(yàn)證，結(jié)果表明1.2V工作電壓下，SRAM能夠在100MHz頻率下進(jìn)行正確的讀寫操作，并具有抗多節(jié)點(diǎn)翻轉(zhuǎn)能力。
[Abstract]:With the rapid development of integrated circuits, the fabrication process size has entered the nanometer level, which makes the integrated circuit system more and more vulnerable to the radiation effects from the ground environment and the space environment, especially the single-particle flip (SEU). The static random access memory (SRAM) occupies an increasingly important position with the development of industry because of its high speed and low power consumption. However, it is also the most sensitive part of integrated circuit system to SEU. Therefore, the industry has been looking for effective SRAM radiation reinforcement technology. Firstly, this paper studies and analyzes the reinforcement schemes of SRAM technology grade, layout level, system level and circuit level, and the working mechanism of each anti-SEU reinforcement storage cell. Based on the fact that these strengthened storage cells have few anti-multi-node flip ability under the current nanometer process size, the improved DICE unit, TDICE cell, is used to design the SRAM. with the capacity of 128x8bit with the anti-multi-node flip ability. In this paper, the performance of TDICE unit and the process of building SMIC65nm standard cell library are studied in detail. TDICE is designed as standard library unit according to the design requirements of the standard unit library, and it can be recognized by EDA tools through verification. Secondly, the design of the peripheral circuit of SRAM is introduced in detail, and the function of each circuit is verified by simulation. Then, the whole circuit of SRAM is built with each part of the circuit and the memory array. Peripheral circuits include column decoding circuit, sensitive amplifier circuit, write control circuit and data input and output circuit. The simulation results show that the SRAM function is correct. Finally, based on SMIC65nm process, the layout and post-simulation of each circuit module and SRAM circuit are designed and implemented. The results show that SRAM can read and write correctly at 100MHz frequency under 1.2 V operating voltage. And it has the ability to resist multi-node flipping.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TP333
本文編號：2351976
[Abstract]:With the rapid development of integrated circuits, the fabrication process size has entered the nanometer level, which makes the integrated circuit system more and more vulnerable to the radiation effects from the ground environment and the space environment, especially the single-particle flip (SEU). The static random access memory (SRAM) occupies an increasingly important position with the development of industry because of its high speed and low power consumption. However, it is also the most sensitive part of integrated circuit system to SEU. Therefore, the industry has been looking for effective SRAM radiation reinforcement technology. Firstly, this paper studies and analyzes the reinforcement schemes of SRAM technology grade, layout level, system level and circuit level, and the working mechanism of each anti-SEU reinforcement storage cell. Based on the fact that these strengthened storage cells have few anti-multi-node flip ability under the current nanometer process size, the improved DICE unit, TDICE cell, is used to design the SRAM. with the capacity of 128x8bit with the anti-multi-node flip ability. In this paper, the performance of TDICE unit and the process of building SMIC65nm standard cell library are studied in detail. TDICE is designed as standard library unit according to the design requirements of the standard unit library, and it can be recognized by EDA tools through verification. Secondly, the design of the peripheral circuit of SRAM is introduced in detail, and the function of each circuit is verified by simulation. Then, the whole circuit of SRAM is built with each part of the circuit and the memory array. Peripheral circuits include column decoding circuit, sensitive amplifier circuit, write control circuit and data input and output circuit. The simulation results show that the SRAM function is correct. Finally, based on SMIC65nm process, the layout and post-simulation of each circuit module and SRAM circuit are designed and implemented. The results show that SRAM can read and write correctly at 100MHz frequency under 1.2 V operating voltage. And it has the ability to resist multi-node flipping.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TP333
【參考文獻(xiàn)】
相關(guān)期刊論文 前3條
1 施亮;高寧;于宗光;;深亞微米SRAM存儲單元靜態(tài)噪聲容限研究[J];電子與封裝;2007年05期
2 徐睿;顧展弘;羅靜;;一種抗輻射加固檢錯糾錯電路的設(shè)計[J];微電子學(xué);2010年04期
3 QIN JunRui;LI DaWei;CHEN ShuMing;;A novel layout for single event upset mitigation in advanced CMOS SRAM cells[J];Science China(Technological Sciences);2013年01期
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