發(fā)布時間：2018-11-02 20:03

【摘要】：隨著集成電路工藝進入深亞微米和超深亞微米階段,芯片的集成度不斷增加,時鐘頻率不斷提高,芯片的整體性能也隨之提升。但由于單位面積上集成的晶體管數(shù)量的持續(xù)增加,芯片的功耗也不斷的攀升。隨著便攜式移動嵌入式系統(tǒng)應用的不斷發(fā)展和普及,低功耗的高性能嵌入式處理器已成為今后移動計算必然的發(fā)展趨勢和發(fā)展要求,而其中高速緩存單元的功耗尤為突出。本文圍繞嵌入式處理器的高速緩存低功耗技術,重點研究了基于路訪問軌跡的低功耗指令高速緩存策略和基于路休眠的低功耗數(shù)據(jù)高速緩存策略。 針對指令高速緩存的連續(xù)訪問特性提出一種基于路訪問軌跡的組相聯(lián)指令高速緩存的低功耗策略。該策略利用改進的指令高速緩存和轉移目標緩存建立和維護運行時指令高速緩存的路訪問軌跡來減少指令高速緩存命中檢測及無關路訪問。進一步提出了基于跨行訪問前驅指針、轉移前驅狀態(tài)、轉移前驅指針及轉移目標索引的路訪問軌跡信息維護策略用以降低信息重建的頻度,從而更有效地利用已建立的路訪問軌跡信息。實驗結果表明,采用優(yōu)化后的路訪問軌跡策略的指令高速緩存的標志存儲器訪問和數(shù)據(jù)存儲器訪問在理想情況下分別降低到傳統(tǒng)指令高速緩存的0.74%和25.55%。 針對數(shù)據(jù)高速緩存緩存的離散訪問特性提出一種基于路休眠的數(shù)據(jù)高速緩存低功耗策略。該策略利用門控電源技術控制數(shù)據(jù)高速緩存行的通斷,消除長期閑置的數(shù)據(jù)高速緩存行的靜態(tài)功耗。同時進一步研究了適用于不同應用的閑置閾值,并進一步提出全局可配的閑置閾值寄存器以適應不同應用對于閑置閾值的不同要求。實驗結果表明,最優(yōu)情況數(shù)據(jù)高速緩存行的靜態(tài)功耗可以降低到9.13%,最差情況可以降低到34.7%。
[Abstract]:With the IC process entering deep submicron and ultra-deep submicron phase, the integration level of the chip is increasing, the clock frequency is increasing, and the overall performance of the chip is also improved. But as the number of transistors integrated per unit area continues to increase, the power consumption of chips is rising. With the continuous development and popularization of portable mobile embedded system applications, low power high performance embedded processors have become the inevitable trend and development requirements of mobile computing in the future, and the power consumption of cache cells is particularly prominent. This paper focuses on the low-power cache strategy based on path access trajectory and low-power data cache strategy based on path sleep. Aiming at the continuous access characteristics of instruction cache, a low power policy of group associated instruction cache based on path access trajectory is proposed. This strategy uses improved instruction cache and transfer target cache to establish and maintain path access trajectory of runtime instruction cache to reduce instruction cache hit detection and irrelevant access. Furthermore, a path access path information maintenance strategy based on cross row access precursor pointer, transfer precursor state, transfer precursor pointer and transfer target index is proposed to reduce the frequency of information reconstruction. Thus, the established path access path information can be used more effectively. The experimental results show that the flag memory access and data memory access of instruction cache using the optimized path access path strategy are reduced to 0.74% and 25.55% of the traditional instruction cache respectively under ideal conditions. According to the discrete access characteristics of data cache, a low power policy for data cache based on path sleep is proposed. The strategy uses the gated power supply technology to control the on-off of the data cache row, and eliminates the static power consumption of the long-idle data cache row. At the same time, the idle threshold for different applications is further studied, and a globally configurable idle threshold register is proposed to meet the different requirements of different applications for idle threshold. The experimental results show that the static power consumption of the optimal data cache row can be reduced to 9.13 and the worst case can be reduced to 34.7.
【學位授予單位】：浙江大學
【學位級別】：碩士
【學位授予年份】：2012
【分類號】：TP333

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本文編號：2306817