【摘要】：集成電路目前仍在按照摩爾定律飛速發(fā)展著，單一芯片晶體管數(shù)目已達(dá)到數(shù)十億、芯片主頻達(dá)到數(shù)G赫茲。目前主流芯片設(shè)計(jì)實(shí)現(xiàn)方法為基于標(biāo)準(zhǔn)單元庫(kù)的半定制設(shè)計(jì)方法，在追求強(qiáng)大的可靠性和通用性時(shí)會(huì)犧牲部分性能。因此，在設(shè)計(jì)高性能處理器時(shí)，標(biāo)準(zhǔn)單元庫(kù)通常難以滿足速度需求。40nm工藝下普通低閾值寄存器延時(shí)大約60ps左右，對(duì)2GHz以上微處理器來(lái)說(shuō)，寄存器延時(shí)已超過(guò)棧間延時(shí)的12%以上，減小寄存器延時(shí)成為提升微處理器性能的關(guān)鍵問(wèn)題。 本文提出并實(shí)現(xiàn)了一類低延時(shí)脈沖寄存器（LDPR，Low Delay Pulse Register），該寄存器使用脈沖鎖存器結(jié)構(gòu)，節(jié)約了一級(jí)鎖存延時(shí)，，在全定制精細(xì)調(diào)整結(jié)構(gòu)與晶體管尺寸的情況下，大大縮短了寄存器的傳播延時(shí)。同時(shí)，本文完成了LDPR寄存器成組和多種驅(qū)動(dòng)能力設(shè)計(jì)以及版圖繪制。版圖模擬結(jié)果表明，本文設(shè)計(jì)并實(shí)現(xiàn)的低延時(shí)脈沖寄存器的傳播延時(shí)比標(biāo)準(zhǔn)單元庫(kù)中的主從邊沿觸發(fā)器減少50%。成組寄存器的組內(nèi)寄存器時(shí)鐘偏差小于0.3ps。 經(jīng)過(guò)特征化的寄存器可以被主流布局布線工具識(shí)別使用，將本文提出的低延時(shí)脈沖寄存器在物理設(shè)計(jì)實(shí)例中進(jìn)行可用性實(shí)驗(yàn)，針對(duì)實(shí)際工程問(wèn)題編寫了腳本，可以讓工具正確的使用此類低延時(shí)寄存器。寄存器在整個(gè)物理設(shè)計(jì)流程中應(yīng)用正常，未出現(xiàn)任何錯(cuò)誤，實(shí)驗(yàn)證明本文提出的LDPR寄存器具有實(shí)用價(jià)值。
[Abstract]:The integrated circuits are still developing rapidly according to Moore's law. The number of single chip transistors has reached billions and the main frequency of chips has reached the number of G hertz. At present, the main chip design method is based on standard cell library semi-custom design method, which will sacrifice some performance while pursuing strong reliability and versatility. Therefore, when designing high performance processor, the standard cell library is difficult to meet the requirement of speed. In 40nm process, the delay of low threshold register is about 60ps, for microprocessor above 2GHz, the delay of register is more than 12% of the delay between stacks. Reducing register delay is a key problem to improve microprocessor performance. In this paper, a class of low delay pulse registers (LDPR,Low Delay Pulse Register),) is proposed and implemented, which uses pulse latch structure, saves the first stage latch delay, and adjusts the structure and transistor size with full customization. The delay of register propagation is greatly reduced. At the same time, this paper completes the LDPR register group and various driving ability design and layout drawing. The layout simulation results show that the propagation delay of the low delay pulse register designed and implemented in this paper is 50% less than that of the master-slave edge flip-flop in the standard cell library. The clock deviation of the group registers is less than 0.3 ps. The characteristic register can be recognized and used by the mainstream layout and routing tool. The low delay pulse register proposed in this paper is tested in the physical design example, and the script is written in view of the actual engineering problem. This low-delay register can be used correctly by the tool. The register is applied normally in the whole physical design process without any errors. The experiment proves that the LDPR register proposed in this paper has practical value.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP332

【參考文獻(xiàn)】

相關(guān)博士學(xué)位論文 前1條

1 李振濤;高性能DSP關(guān)鍵電路及EDA技術(shù)研究[D];國(guó)防科學(xué)技術(shù)大學(xué);2007年

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