發(fā)布時間：2018-10-16 18:40

【摘要】：隨著計算機性能的不斷提高，CPU的時鐘頻率以及計算機外圍接口的帶寬成指數(shù)地增長，這導致處理器的數(shù)據(jù)吞吐量也相應(yīng)的增加。作為第二代總線標準代表的PCI和PCI-X總線，其局限性越來越明顯，尤其在帶寬和擴展性方面，已經(jīng)不能滿足系統(tǒng)日益增長的需求。PCI Express總線應(yīng)運而生，，其先進的系統(tǒng)架構(gòu)、靈活的擴展性和超高的帶寬，使得PCI Express迅速適應(yīng)高速及實時性要求比較高場合，并且會在未來幾年內(nèi)成為總線領(lǐng)域的佼佼者。 本課題的主要成果是設(shè)計了一種實現(xiàn)PCI Express總線接口和光纖通信模塊的硬件系統(tǒng)。該系統(tǒng)以一片高性能的Virtex-6FPGA為核心，物理結(jié)構(gòu)依據(jù)PCI Express2.0標準設(shè)計，PCI Express總線最多可以擴展到8個通道，理論可支持的最大帶寬為40Gbps。同時，系統(tǒng)對外提供可替換的IO接口模塊，通過接插光纖模塊可以實現(xiàn)主機與外設(shè)之間的高速數(shù)據(jù)傳輸。 首先，對包括PCI Express總線在內(nèi)的三代總線標準的性能指標進行了對比，歸結(jié)出PCI Express總線的技術(shù)優(yōu)勢，并預測了其未來的發(fā)展趨勢。對PCI Express總線標準的系統(tǒng)架構(gòu)、層次結(jié)構(gòu)、事務(wù)機制以及配置空間進行了詳細的分析，并總結(jié)了課題研究時涉及到的關(guān)鍵技術(shù)和知識點。 然后，詳細論述了FPGA系統(tǒng)的硬件設(shè)計方案和邏輯設(shè)計方案。前者主要包括對系統(tǒng)硬件的總體方案設(shè)計和板卡級設(shè)計；后者對于系統(tǒng)邏輯設(shè)計中比較核心的模塊，如PCI Express的DMA數(shù)據(jù)傳輸方式、基于Aurora協(xié)議的光纖通信方式等，進行了細致的分析，并在文中給出了時序轉(zhuǎn)換圖和Verilog代碼。 最后，用Modelsim和Chipscope工具對設(shè)計方案進行了時序仿真和驗證，以保證設(shè)計的合理性和正確性。通過驗證結(jié)果可以證明上述方案是可行的。
[Abstract]:With the continuous improvement of computer performance, the clock frequency of CPU and the bandwidth of computer peripheral interface increase exponentially, which leads to the corresponding increase in data throughput of the processor. The limitation of PCI and PCI-X bus, which is the representative of the second generation bus standard, is becoming more and more obvious. Especially in the aspect of bandwidth and expansibility, the. PCI Express bus has been unable to meet the increasing demand of the system, and its advanced system architecture has come into being. Flexible expansibility and ultra-high bandwidth enable PCI Express to adapt to high speed and real-time requirements rapidly and will become the best in the field of bus in the next few years. The main achievement of this thesis is to design a hardware system to realize PCI Express bus interface and optical fiber communication module. The system is based on a high-performance Virtex-6FPGA. The physical structure of the system is designed according to the PCI Express2.0 standard. The, PCI Express bus can be extended to 8 channels at most, and the maximum bandwidth supported by the theory is 40Gbps. At the same time, the system provides the replaceable IO interface module, which can realize the high-speed data transmission between the host computer and the peripheral device by plugging in the optical fiber module. Firstly, the performance indexes of three generation bus standards, including PCI Express bus, are compared, the technical advantages of PCI Express bus are summed up, and the future development trend of PCI Express bus is predicted. The system architecture, hierarchy, transaction mechanism and configuration space of PCI Express bus standard are analyzed in detail, and the key technologies and knowledge points involved in the research are summarized. Then, the hardware design and logic design of FPGA system are discussed in detail. The former mainly includes the overall scheme design of the system hardware and the board level design, while the latter includes the core modules in the system logic design, such as the DMA data transmission mode of PCI Express, the optical fiber communication mode based on the Aurora protocol, etc. Detailed analysis is carried out, and the timing conversion diagram and Verilog code are given in this paper. Finally, the design scheme is simulated and verified with Modelsim and Chipscope tools to ensure the rationality and correctness of the design. The experimental results show that the proposed scheme is feasible.
【學位授予單位】：燕山大學
【學位級別】：碩士
【學位授予年份】：2013
【分類號】：TP336

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