【摘要】：隨著計(jì)算機(jī)性能的不斷提高，CPU的時(shí)鐘頻率以及計(jì)算機(jī)外圍接口的帶寬成指數(shù)地增長，這導(dǎo)致處理器的數(shù)據(jù)吞吐量也相應(yīng)的增加。作為第二代總線標(biāo)準(zhǔn)代表的PCI和PCI-X總線，其局限性越來越明顯，尤其在帶寬和擴(kuò)展性方面，已經(jīng)不能滿足系統(tǒng)日益增長的需求。PCI Express總線應(yīng)運(yùn)而生，，其先進(jìn)的系統(tǒng)架構(gòu)、靈活的擴(kuò)展性和超高的帶寬，使得PCI Express迅速適應(yīng)高速及實(shí)時(shí)性要求比較高場(chǎng)合，并且會(huì)在未來幾年內(nèi)成為總線領(lǐng)域的佼佼者。 本課題的主要成果是設(shè)計(jì)了一種實(shí)現(xiàn)PCI Express總線接口和光纖通信模塊的硬件系統(tǒng)。該系統(tǒng)以一片高性能的Virtex-6FPGA為核心，物理結(jié)構(gòu)依據(jù)PCI Express2.0標(biāo)準(zhǔn)設(shè)計(jì)，PCI Express總線最多可以擴(kuò)展到8個(gè)通道，理論可支持的最大帶寬為40Gbps。同時(shí)，系統(tǒng)對(duì)外提供可替換的IO接口模塊，通過接插光纖模塊可以實(shí)現(xiàn)主機(jī)與外設(shè)之間的高速數(shù)據(jù)傳輸。 首先，對(duì)包括PCI Express總線在內(nèi)的三代總線標(biāo)準(zhǔn)的性能指標(biāo)進(jìn)行了對(duì)比，歸結(jié)出PCI Express總線的技術(shù)優(yōu)勢(shì)，并預(yù)測(cè)了其未來的發(fā)展趨勢(shì)。對(duì)PCI Express總線標(biāo)準(zhǔn)的系統(tǒng)架構(gòu)、層次結(jié)構(gòu)、事務(wù)機(jī)制以及配置空間進(jìn)行了詳細(xì)的分析，并總結(jié)了課題研究時(shí)涉及到的關(guān)鍵技術(shù)和知識(shí)點(diǎn)。 然后，詳細(xì)論述了FPGA系統(tǒng)的硬件設(shè)計(jì)方案和邏輯設(shè)計(jì)方案。前者主要包括對(duì)系統(tǒng)硬件的總體方案設(shè)計(jì)和板卡級(jí)設(shè)計(jì)；后者對(duì)于系統(tǒng)邏輯設(shè)計(jì)中比較核心的模塊，如PCI Express的DMA數(shù)據(jù)傳輸方式、基于Aurora協(xié)議的光纖通信方式等，進(jìn)行了細(xì)致的分析，并在文中給出了時(shí)序轉(zhuǎn)換圖和Verilog代碼。 最后，用Modelsim和Chipscope工具對(duì)設(shè)計(jì)方案進(jìn)行了時(shí)序仿真和驗(yàn)證，以保證設(shè)計(jì)的合理性和正確性。通過驗(yàn)證結(jié)果可以證明上述方案是可行的。
[Abstract]:With the continuous improvement of computer performance, the clock frequency of CPU and the bandwidth of computer peripheral interface increase exponentially, which leads to the corresponding increase in data throughput of the processor. The limitation of PCI and PCI-X bus, which is the representative of the second generation bus standard, is becoming more and more obvious. Especially in the aspect of bandwidth and expansibility, the. PCI Express bus has been unable to meet the increasing demand of the system, and its advanced system architecture has come into being. Flexible expansibility and ultra-high bandwidth enable PCI Express to adapt to high speed and real-time requirements rapidly and will become the best in the field of bus in the next few years. The main achievement of this thesis is to design a hardware system to realize PCI Express bus interface and optical fiber communication module. The system is based on a high-performance Virtex-6FPGA. The physical structure of the system is designed according to the PCI Express2.0 standard. The, PCI Express bus can be extended to 8 channels at most, and the maximum bandwidth supported by the theory is 40Gbps. At the same time, the system provides the replaceable IO interface module, which can realize the high-speed data transmission between the host computer and the peripheral device by plugging in the optical fiber module. Firstly, the performance indexes of three generation bus standards, including PCI Express bus, are compared, the technical advantages of PCI Express bus are summed up, and the future development trend of PCI Express bus is predicted. The system architecture, hierarchy, transaction mechanism and configuration space of PCI Express bus standard are analyzed in detail, and the key technologies and knowledge points involved in the research are summarized. Then, the hardware design and logic design of FPGA system are discussed in detail. The former mainly includes the overall scheme design of the system hardware and the board level design, while the latter includes the core modules in the system logic design, such as the DMA data transmission mode of PCI Express, the optical fiber communication mode based on the Aurora protocol, etc. Detailed analysis is carried out, and the timing conversion diagram and Verilog code are given in this paper. Finally, the design scheme is simulated and verified with Modelsim and Chipscope tools to ensure the rationality and correctness of the design. The experimental results show that the proposed scheme is feasible.
【學(xué)位授予單位】：燕山大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP336

【參考文獻(xiàn)】

相關(guān)期刊論文 前10條

1 王紅;彭亮;于宗光;;FPGA現(xiàn)狀與發(fā)展趨勢(shì)[J];電子與封裝;2007年07期

2 秦志輝;龔華達(dá);覃勇;;基于FPGA的CPCI總線光纖傳輸系統(tǒng)[J];光通信技術(shù);2008年04期

3 李欣;管紹軍;胡曉天;;基于FPGA的光纖通信系統(tǒng)的設(shè)計(jì)與實(shí)現(xiàn)[J];電子設(shè)計(jì)工程;2012年08期

4 徐天;何道君;徐金甫;;基于IP核的PCI Express接口[J];計(jì)算機(jī)工程;2009年24期

5 賴聯(lián)有;陳僅星;許偉堅(jiān);;基于LTspice Ⅳ的開關(guān)電源設(shè)計(jì)及仿真[J];通信電源技術(shù);2010年01期

6 石峰;吳建飛;劉凱;徐欣;;基于Xilinx FPGA的PCIE接口實(shí)現(xiàn)[J];微處理機(jī);2008年06期

7 林錦棠;敖發(fā)良;;PCI Express研究及基于FPGA的實(shí)現(xiàn)[J];微計(jì)算機(jī)信息;2008年29期

8 汪精華;胡善清;龍騰;;基于FPGA實(shí)現(xiàn)的PCIE協(xié)議的DMA讀寫模塊[J];微計(jì)算機(jī)信息;2010年29期

9 費(fèi)瑋瑋;王長清;劉濮鯤;蔡惠智;;基于PCI-Express總線高速光纖傳輸系統(tǒng)的實(shí)現(xiàn)[J];微計(jì)算機(jī)信息;2010年29期

10 沈輝;張萍;;FPGA在PCI Express總線接口中的應(yīng)用[J];現(xiàn)代電子技術(shù);2010年14期

相關(guān)碩士學(xué)位論文 前3條

1 劉煜峰;基于FPGA的多通道DMA控制器的IP核設(shè)計(jì)[D];華北電力大學(xué)（北京）;2008年

2 李中偉;LDO線性穩(wěn)壓器的研究與設(shè)計(jì)[D];西北大學(xué);2009年

3 吳帥;基于PCI Express總線和光模塊的高速串行傳輸系統(tǒng)設(shè)計(jì)與實(shí)現(xiàn)[D];國防科學(xué)技術(shù)大學(xué);2008年

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