多線程微處理器指令雙發(fā)射結(jié)構(gòu)的設(shè)計與實現(xiàn)
[Abstract]:T2 processor is a multi-core multi-thread processor. Each processor core consists of eight threads, divided into two groups, with fine-grained multithreading and simultaneous multithreading between groups. T2 each thread group sends only one instruction per cycle. Therefore, for a single thread, the IPC (Instruction Per Cycle) does not exceed 1, which makes T 2 single thread performance lower. Single-thread performance is an important factor to be considered in processor design. On the one hand, because many applications are serial programs, their execution speed depends on the performance of a single thread; on the other hand, there are always parts of parallel programs that cannot be parallelized, and this part still needs serial execution. Therefore, it is of great significance to improve the performance of single-thread. In this paper, based on T2 processor, we improve the structure of dual transmission to support single thread and double transmission, so as to improve the performance of single thread. The main work of this paper is as follows: 1. Based on T2, a single-threaded dual-firing structure is designed and implemented to develop single-threaded instruction level parallelism and improve single-thread performance; 2. The function verification and performance evaluation scheme of dual-launch structure is proposed, the software simulation platform is built and the function model of simulation is established, the function verification points are extracted and the test incentives for function verification are compiled. 3. The function verification and performance evaluation of single-thread dual-launch structure are carried out on the software simulation platform. The results show that the design and implementation of the single thread dual emission structure can achieve the expected function and improve the performance of the single thread effectively.
【學(xué)位授予單位】:國防科學(xué)技術(shù)大學(xué)
【學(xué)位級別】:碩士
【學(xué)位授予年份】:2013
【分類號】:TP332
【參考文獻】
相關(guān)期刊論文 前9條
1 張民選;王永文;邢座程;鄧讓鈺;蔣江;張承義;;高性能通用微處理器體系結(jié)構(gòu)關(guān)鍵技術(shù)研究[J];計算機研究與發(fā)展;2006年06期
2 王永文;鄭倩冰;尹遠;孫彩霞;竇強;;細粒度多線程處理器中前瞻性數(shù)據(jù)加載的設(shè)計與實現(xiàn)[J];計算機研究與發(fā)展;2011年S1期
3 周國昌,王忠,車德亮,馮國臣;一種改進的嵌入式SIMD協(xié)處理器設(shè)計[J];計算機工程與應(yīng)用;2004年31期
4 任建;安虹;路放;梁博;;同時多線程處理器上的動態(tài)分支預(yù)測器設(shè)計方案研究[J];計算機科學(xué);2006年03期
5 印杰;江建慧;;緩解同時多線程結(jié)構(gòu)中線程對關(guān)鍵資源的競爭[J];計算機科學(xué);2010年03期
6 馮華;唐宏偉;盧凱;劉勇鵬;;OpenSparc T2處理器虛擬化技術(shù)研究[J];計算機工程與科學(xué);2010年07期
7 孫彩霞;張民選;;使用取指策略控制同時多線程處理器中個體線程的性能[J];計算機學(xué)報;2008年02期
8 劉星江;王慧;;一種基于Verilog的驗證平臺搭建及應(yīng)用[J];信息安全與通信保密;2013年01期
9 劉成;張凱;陳建勛;;混合方式數(shù)據(jù)驗證方案的研究[J];計算機工程與設(shè)計;2013年01期
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