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多線程微處理器指令雙發(fā)射結(jié)構(gòu)的設(shè)計(jì)與實(shí)現(xiàn)

發(fā)布時(shí)間:2018-10-16 18:26
【摘要】:T2處理器是一款多核多線程處理器。每個(gè)處理器核包含8個(gè)線程,分成兩組,組內(nèi)采用細(xì)粒度多線程,組間采用同時(shí)多線程。T2每個(gè)線程組每個(gè)周期只發(fā)射一條指令執(zhí)行,因此對(duì)單線程而言IPC(Instruction Per Cycle)不會(huì)超過(guò)1,這使得T2的單線程性能較低。 單線程性能是處理器設(shè)計(jì)中需要考慮的重要因素。一方面,由于很多應(yīng)用程序都是串行程序,其執(zhí)行速度依賴于單線程的性能;另一方面,并行程序中總有不能并行化的部分,這一部分仍然需要串行執(zhí)行。因此提高單線程性能具有重要的意義。 本文以T2處理器為基礎(chǔ),對(duì)雙發(fā)射結(jié)構(gòu)進(jìn)行改進(jìn),使其支持單線程雙發(fā)射,以提高單線程的性能。論文的主要工作有: 1.基于T2設(shè)計(jì)并實(shí)現(xiàn)了單線程雙發(fā)射結(jié)構(gòu),以開發(fā)單線程的指令級(jí)并行、提高單線程性能; 2.提出雙發(fā)射結(jié)構(gòu)的功能驗(yàn)證和性能評(píng)估方案,搭建了軟件模擬平臺(tái)并建立了模擬需要的功能模型,提取了功能驗(yàn)證點(diǎn)并據(jù)此編寫了功能驗(yàn)證需要的測(cè)試激勵(lì); 3.在搭建的軟件模擬平臺(tái)上對(duì)單線程雙發(fā)射結(jié)構(gòu)進(jìn)行了功能驗(yàn)證和性能評(píng)估。結(jié)果表明,,論文設(shè)計(jì)并實(shí)現(xiàn)的單線程雙發(fā)射結(jié)構(gòu)實(shí)現(xiàn)了預(yù)期的功能,有效提高了單線程的性能。
[Abstract]:T2 processor is a multi-core multi-thread processor. Each processor core consists of eight threads, divided into two groups, with fine-grained multithreading and simultaneous multithreading between groups. T2 each thread group sends only one instruction per cycle. Therefore, for a single thread, the IPC (Instruction Per Cycle) does not exceed 1, which makes T 2 single thread performance lower. Single-thread performance is an important factor to be considered in processor design. On the one hand, because many applications are serial programs, their execution speed depends on the performance of a single thread; on the other hand, there are always parts of parallel programs that cannot be parallelized, and this part still needs serial execution. Therefore, it is of great significance to improve the performance of single-thread. In this paper, based on T2 processor, we improve the structure of dual transmission to support single thread and double transmission, so as to improve the performance of single thread. The main work of this paper is as follows: 1. Based on T2, a single-threaded dual-firing structure is designed and implemented to develop single-threaded instruction level parallelism and improve single-thread performance; 2. The function verification and performance evaluation scheme of dual-launch structure is proposed, the software simulation platform is built and the function model of simulation is established, the function verification points are extracted and the test incentives for function verification are compiled. 3. The function verification and performance evaluation of single-thread dual-launch structure are carried out on the software simulation platform. The results show that the design and implementation of the single thread dual emission structure can achieve the expected function and improve the performance of the single thread effectively.
【學(xué)位授予單位】:國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】:碩士
【學(xué)位授予年份】:2013
【分類號(hào)】:TP332

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