【摘要】：邊界掃描技術(shù)是一種標(biāo)準(zhǔn)的數(shù)字系統(tǒng)測試及可測性設(shè)計方法，它在工業(yè)界得到了廣泛的應(yīng)用。但是隨著電子技術(shù)和高速數(shù)字通信技術(shù)的飛速發(fā)展，為了提高信號的傳輸速率，高速接口的使用越來越廣泛。第一部邊界掃描技術(shù)標(biāo)準(zhǔn)為IEEEStd1149.1，它主要是針對芯片內(nèi)部互連和芯片與PCB板之間的低速數(shù)字信號的測試，但是對高級數(shù)字網(wǎng)絡(luò)中交流耦合差分信號的測試，，則表現(xiàn)出明顯的不足。從而導(dǎo)致測試覆蓋率大大的降低。在這種情況下，2003年IEEE通過了IEEE Std1149.6標(biāo)準(zhǔn)，這一標(biāo)準(zhǔn)主要是解決1149.1中無法檢測的故障。雖然1149.6標(biāo)準(zhǔn)早在2001年就已經(jīng)形成，但是由于標(biāo)準(zhǔn)需要向下兼容和處理交流特性的信號等特點，使得電路實現(xiàn)起來非常的困難，到目前為止，只有幾款芯片真正實現(xiàn)這一技術(shù)。 本文主要對邊界掃描技術(shù)和具有交流耦合差分特性的信號進(jìn)行了理論分析和研究，針對PCIE高速接口芯片實現(xiàn)邊界掃描設(shè)計。 1、詳細(xì)分析了IEEE1149.6標(biāo)準(zhǔn)中針對交流耦合差分信號的邊界掃描設(shè)計方法，提出了針對高速接口PCIE芯片的邊界掃描設(shè)計方案并進(jìn)行了電路邏輯設(shè)計，主要包括數(shù)字驅(qū)動器模塊、數(shù)字接收器模塊、模擬測試接收器模塊和1149.6測試訪問端口TAP。 2、采用全定制的方法實現(xiàn)了邊界掃描電路中的數(shù)字驅(qū)動器模塊和數(shù)字接收器模塊的版圖設(shè)計。 本文還分別對邊界掃描設(shè)計電路中的指令集、交流測試信號和模塊的版圖設(shè)計進(jìn)行了模擬驗證。模擬結(jié)果表明，該邊界掃描設(shè)計是正確的。
[Abstract]:Boundary scan technology is a standard method of digital system testing and testability design. It has been widely used in industry. However, with the rapid development of electronic technology and high-speed digital communication technology, in order to improve the signal transmission rate, high-speed interface is more and more widely used. The first boundary scan standard is IEEEStd1149.1, which is mainly used to test the low speed digital signal between the chip and the PCB board. However, the test of the AC coupled differential signal in the advanced digital network is obviously inadequate. This results in a significant reduction in test coverage. In this case, IEEE adopted the IEEE Std1149.6 standard in 2003, which mainly addresses undetectable faults in 1149.1. Although the 1149.6 standard was formed as early as 2001, it is very difficult to realize the circuit because the standard needs to be compatible down and the signal of AC characteristic is processed. So far, only a few chips have realized this technology. In this paper, the boundary scan technique and the signal with AC coupling difference characteristics are analyzed and studied theoretically. The design of boundary scan for PCIE high-speed interface chip is introduced. 1. The design method of boundary scan for AC coupled differential signal in IEEE1149.6 standard is analyzed in detail. The design scheme of boundary scan for PCIE chip with high speed interface is put forward and the circuit logic design is carried out, which includes digital driver module and digital receiver module. Simulation test receiver module and 1149.6 test access port TAP. 2 are used to realize the layout design of digital driver module and digital receiver module in the boundary scan circuit. The instruction set, AC test signal and layout design of the circuit are simulated and verified in this paper. The simulation results show that the boundary scan design is correct.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP334.7

【共引文獻(xiàn)】

相關(guān)期刊論文 前1條

1 周杰;周紹磊;彭賢;雷鳴;;邊界掃描技術(shù)在板級可測性設(shè)計中的應(yīng)用[J];中國測試技術(shù);2007年04期

相關(guān)碩士學(xué)位論文 前10條

1 王哲;IRFPA讀出電路設(shè)計測試及可測性設(shè)計研究[D];北京交通大學(xué);2010年

2 代桃;多板卡電子系統(tǒng)的可測性設(shè)計與實現(xiàn)[D];電子科技大學(xué);2011年

3 楊

本文編號：2274087