【摘要】：隨著通信技術(shù)以及微電子產(chǎn)業(yè)的不斷發(fā)展，網(wǎng)絡(luò)應(yīng)用也在不斷更新。網(wǎng)絡(luò)帶寬的急劇增長(zhǎng)和網(wǎng)絡(luò)協(xié)議的不斷更新，使得傳統(tǒng)的網(wǎng)絡(luò)設(shè)備方案已經(jīng)不能滿足用戶對(duì)于高性能和可編程方面的需求。傳統(tǒng)的網(wǎng)絡(luò)設(shè)備像通用處理器（GPP）雖然靈活性好、成本低，但由于它性能低下，所以不適合處理高速網(wǎng)絡(luò)流量；ASIC（ApplicationSpecificIntegratedCircuit）雖然性能高，采用硬件的方式能夠?qū)崿F(xiàn)各種成熟的網(wǎng)絡(luò)功能，，但由于它的設(shè)計(jì)周期長(zhǎng)，靈活性較差，而且費(fèi)用高；FPGA(FieldProgrammableGateArray)雖然可反復(fù)編程，能在一定程度上靈活的擴(kuò)展業(yè)務(wù)類型，但由于受技術(shù)限制還不成熟。而ASIP（ApplicationSpecificInstructionProcessor）也就是網(wǎng)絡(luò)處理器（NP）結(jié)合了上述傳統(tǒng)設(shè)備的優(yōu)點(diǎn)，由若干微處理器和一些硬件協(xié)處理器組成，并行工作，通過軟件來控制處理流程。它具有可編程可擴(kuò)展的特性，實(shí)現(xiàn)了業(yè)務(wù)靈活性與高性能的有效結(jié)合。 本文中所設(shè)計(jì)的DRAM存儲(chǔ)控制器，采用多種優(yōu)化策略，以便充分提升網(wǎng)絡(luò)處理器的其他主設(shè)備對(duì)存儲(chǔ)器的訪問效率。由于XDNP采用異構(gòu)多核硬件多線程的設(shè)計(jì)結(jié)構(gòu)，所以它的多個(gè)包處理引擎（PE）以及每個(gè)包處理引擎的多個(gè)線程需要不斷的對(duì)片外的DRAM存儲(chǔ)器進(jìn)行訪問。由于同一時(shí)刻只能有一個(gè)包處理引擎的一個(gè)線程對(duì)DRAM芯片進(jìn)行訪問，所以對(duì)DRAM芯片的訪問延時(shí)就成了決定網(wǎng)絡(luò)處理器性能的最關(guān)鍵的因素。本文所設(shè)計(jì)的DRAM存儲(chǔ)控制器針對(duì)XDNP多核共享的訪存特性，采用一種流水線結(jié)構(gòu)來實(shí)現(xiàn)對(duì)不同部件對(duì)DRAM芯片的訪存指令的處理，大大提升了DRAM控制器的訪存效率以及運(yùn)行頻率，使得DRAM控制器的吞吐率提升了3.6倍，平均延時(shí)下降了50%。運(yùn)行頻率從200M提升到220M，提高了1.1倍。此外設(shè)計(jì)中還對(duì)不同設(shè)備發(fā)出的訪存指令的仲裁進(jìn)行了優(yōu)化，采用基于Round-Robin的混合優(yōu)先級(jí)的仲裁策略動(dòng)態(tài)調(diào)整各類訪存指令的優(yōu)先級(jí)，極大的提高了DRAM控制器的效率。
[Abstract]:With the continuous development of communication technology and microelectronics industry, network applications are constantly updated. With the rapid growth of network bandwidth and the continuous updating of network protocols, the traditional network equipment solutions can no longer meet the needs of users in terms of high performance and programmable. Although traditional network devices such as (GPP) have good flexibility and low cost, but because of its low performance, it is not suitable for processing high-speed network traffic; ASIC (ApplicationSpecificIntegratedCircuit). Although the performance of; ASIC (ApplicationSpecificIntegratedCircuit) is high, it can realize all kinds of mature network functions by hardware. However, because of its long design cycle, low flexibility and high cost; FPGA (FieldProgrammableGateArray), although it can be programmed repeatedly, it can extend the service type flexibly to some extent, but it is not mature because of the technical limitation. ASIP (ApplicationSpecificInstructionProcessor), which is the network processor (NP), combines the advantages of the traditional devices mentioned above. It is composed of several microprocessors and some hardware coprocessors. It works in parallel and controls the processing flow through software. It has the characteristic of programmable and extensible, and realizes the effective combination of business flexibility and high performance. The DRAM storage controller designed in this paper adopts various optimization strategies in order to fully improve the memory access efficiency of other main devices of the network processor. Because XDNP adopts the design structure of heterogeneous multi-core hardware multithreading, its multiple packet processing engine (PE) and multiple threads of each packet processing engine need to continuously access the off-chip DRAM memory. Since only one thread of one packet processing engine can access the DRAM chip at any one time, the delay of access to the DRAM chip becomes the most critical factor that determines the performance of the network processor. The DRAM memory controller designed in this paper aims at the memory access characteristics of XDNP multi-core sharing, and adopts a pipeline structure to process the memory access instructions of different components to the DRAM chip, which greatly improves the memory access efficiency and the running frequency of the DRAM controller. The throughput of the DRAM controller is increased by 3. 6 times, and the average delay is reduced by 50 times. The operating frequency increased 1.1 times from 200m to 220m. In addition, the arbitration of memory access instructions issued by different devices is optimized. The arbitration strategy based on mixed priority of Round-Robin is used to dynamically adjust the priority of all kinds of memory access instructions, which greatly improves the efficiency of DRAM controller.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP332

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