【摘要】：工藝的發(fā)展使得處理器的速度不斷加快,采用流水線、超標量和超長指令字等設計方法使得處理器越來越復雜,這些變化對寄存器堆提出了更高的要求,使得寄存器堆不僅需要具有較高的性能和較小的功耗而且需要具有多端口讀寫能力。而且,隨著工藝的進步,工藝波動導致的影響越來越嚴重,尤其對于寄存器堆這種決定處理器性能的部件的影響尤為明顯,所以要求寄存器堆同時也具有較高的魯棒性。此外,由于醫(yī)學及無線傳感器等領(lǐng)域的發(fā)展,要求處理器可以工作于更低電壓以大幅度減小功耗,所以低電壓寄存器堆設計成為一個重要的研究課題。本文主要側(cè)重于設計高性能、低功耗、多端口的寄存器堆,并對亞閾值電壓下多端口寄存器堆進行了研究與設計。 本文采用全定制的設計方法,在TSMC65nm CMOS LP工藝下,對寄存器堆的設計進行了深入的研究,設計并實現(xiàn)了具有4個讀端口2個寫端口32x32b規(guī)模寄存器堆。 本文首先對寄存器堆進行了初步的研究設計,提出了可以減小功耗并增強魯棒性的寄存器堆輸出模塊,芯片測試結(jié)果顯示該版本的寄存器堆可以非常穩(wěn)定的工作。在1.2V電壓下,功耗僅7.2mW。同時設計了一種采用靈敏放大器結(jié)構(gòu)的寄存器堆,并提出了可以改變讀位線擺幅的結(jié)構(gòu)。 其次本文深入研究并設計了采用更小面積的存儲單元和時鐘脈沖控制字線的方式,實現(xiàn)了一款面積僅0.01mm2的寄存器堆。芯片測試結(jié)果顯示,在1.2V情況下,芯片的工作頻率為1.56GHz下,寄存器堆消耗功耗11.8mW。若不考慮建立時間等因素,則1.2V下寄存器堆最高工作頻率約為2GHz。 本文最后對亞閾值電壓下的寄存器堆進行了研究與設計。首先對亞閾值下CMOS的工作狀態(tài)進行了分析,然后基于亞閾值電壓下CMOS電路的工作狀態(tài),提出了新的存儲單元,并采用與之前完全不同的讀寫方法設計了多端口的寄存器堆。
[Abstract]:With the development of technology, the speed of processor is speeding up. The design methods such as pipeline, superscalar and ultra-long instruction word make the processor more and more complex. These changes put forward higher requirements to register file. The register file needs not only high performance and low power consumption, but also multi-port reading and writing ability. Moreover, with the progress of process, the effect of process fluctuation is becoming more and more serious, especially for register file, which determines the processor performance, so the register file is required to be robust at the same time. In addition, due to the development of medicine and wireless sensor, it is required that the processor can work at lower voltage to greatly reduce power consumption, so the design of low voltage register file has become an important research topic. This paper focuses on the design of high performance, low power, multi-port register file, and the research and design of multi-port register file under sub-threshold voltage. In this paper, the design of register file is deeply studied under the TSMC65nm CMOS LP technology, and the 32x32b size register file with 4 read ports and 2 write ports is designed and implemented. In this paper, a register file output module is proposed, which can reduce the power consumption and enhance the robustness. The chip test results show that this version of the register file can work very stably. At 1.2V, the power consumption is only 7.2 MW. At the same time, a register file with sensitive amplifier structure is designed, and a structure that can change the reading line swing is proposed. Secondly, this paper deeply studies and designs a register file with an area of 0.01mm2 only by using a smaller memory cell and a clock pulse control word line. The chip test results show that under the condition of 1.2 V, the working frequency of the chip is 1.56GHz, and the power consumption of register file is 11.8 MW. If the establishment time is not taken into account, the maximum operating frequency of the register file at 1.2 V is about 2 GHz. At the end of this paper, the register file under sub-threshold voltage is studied and designed. First, the working state of CMOS under sub-threshold voltage is analyzed, then based on the working state of CMOS circuit under sub-threshold voltage, a new memory cell is proposed, and a multi-port register file is designed by using a completely different reading and writing method than before.
【學位授予單位】：復旦大學
【學位級別】：碩士
【學位授予年份】：2012
【分類號】：TP332.11

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相關(guān)碩士學位論文 前4條

1 李毅;高性能低功耗SoC設計以及寄存器堆的應用[D];復旦大學;2011年

2 董方元;寄存器文件的可測性設計與實現(xiàn)[D];復旦大學;2011年

3 張能;600MHz多端口寄存器文件的設計與實現(xiàn)[D];國防科學技術(shù)大學;2008年

4 熊保玉;高性能低功耗多端口寄存器文件研究與全定制實現(xiàn)[D];復旦大學;2011年

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本文編號：2269806