【摘要】：存儲(chǔ)器是計(jì)算機(jī)系統(tǒng)的重要組成部分，是決定計(jì)算機(jī)系統(tǒng)性能的關(guān)鍵設(shè)備之一。隨著半導(dǎo)體技術(shù)的發(fā)展以及集成電路制造工藝的進(jìn)步，“存儲(chǔ)墻”問題變得更加嚴(yán)重，存儲(chǔ)器難以滿足處理器對(duì)數(shù)據(jù)訪問和存儲(chǔ)的高速度、高帶寬、大容量的需求，限制了計(jì)算機(jī)系統(tǒng)的性能。DDR3SDRAM作為新一代的DDR內(nèi)存，以其大容量、高速率和良好的兼容性在許多領(lǐng)域得到了廣泛的應(yīng)用。針對(duì)DDR3控制器的研究已成為當(dāng)前計(jì)算機(jī)領(lǐng)域關(guān)注的焦點(diǎn)。FPGA作為可編程的邏輯器件具有結(jié)構(gòu)靈活，集成度高以及開發(fā)周期短等特點(diǎn)。FPGA的快速發(fā)展加速了其在產(chǎn)品設(shè)計(jì)、原型驗(yàn)證等方面的應(yīng)用。 本文分析了當(dāng)前存儲(chǔ)控制器的研究與發(fā)展情況，研究了DDR3技術(shù)規(guī)范JEDEC-79-3A以及相關(guān)資料。在全面掌握DDR3的結(jié)構(gòu)、技術(shù)規(guī)范以及工作原理的基礎(chǔ)上，提出了一種基于Altera公司FPGA的DDR3控制器設(shè)計(jì)方案。該方案將DDR3控制器分為控制器傳輸層和物理層兩個(gè)部分進(jìn)行設(shè)計(jì)，對(duì)各部分內(nèi)部模塊的功能和邏輯實(shí)現(xiàn)方式進(jìn)行了詳細(xì)的描述。本文從DDR3控制器的設(shè)計(jì)與驗(yàn)證等方面展開研究，，主要工作以及研究成果： 1.對(duì)DRAM的結(jié)構(gòu)和工作原理接口進(jìn)行了深入研究與分析，對(duì)DDR3的新特性、低功耗設(shè)計(jì)技術(shù)等進(jìn)行了詳細(xì)說明。對(duì)DDR3的工作原理和工作過程有了深入的理解。 2.把DDR3內(nèi)存控制器的結(jié)構(gòu)劃分為傳輸層和物理層兩個(gè)部分，使用Verilog對(duì)兩個(gè)部分中的模塊進(jìn)行設(shè)計(jì)。使用Modelsim-Altera對(duì)控制器整體設(shè)計(jì)進(jìn)行了功能仿真。 3.搭建了FPGA驗(yàn)證平臺(tái)，介紹了DDR3控制器的FPGA實(shí)現(xiàn)過程，對(duì)控制器進(jìn)行了讀寫功能驗(yàn)證以及自檢測模型測試。 4.對(duì)內(nèi)存控制策略進(jìn)行了分析，提出了采用體內(nèi)訪存順序調(diào)度的方法對(duì)訪存延時(shí)進(jìn)行優(yōu)化的方法。
[Abstract]:Memory is an important part of computer system and one of the key equipments to determine the performance of computer system. With the development of semiconductor technology and the progress of IC manufacturing technology, the problem of "storage wall" becomes more and more serious, and the memory is difficult to meet the high speed, high bandwidth and large capacity of the processor for data access and storage. As a new generation of DDR memory, DDR3 SDRAM, which limits the performance of computer system, has been widely used in many fields with its large capacity, high speed and good compatibility. The research of DDR3 controller has become the focus in the field of computer. As a programmable logic device, it has the characteristics of flexible structure, high integration and short development cycle. The rapid development of FPGA accelerates its product design. Prototype verification and other applications. In this paper, the current research and development of memory controller are analyzed, and the DDR3 specification JEDEC-79-3A and related data are studied. On the basis of mastering the structure, technical specification and working principle of DDR3, a design scheme of DDR3 controller based on FPGA of Altera Company is presented. In this scheme, the DDR3 controller is divided into two parts: the controller transport layer and the physical layer. The function and logic implementation of each module are described in detail. In this paper, the design and verification of DDR3 controller are studied. The main work and research results are as follows: 1. The structure and working principle interface of DRAM are deeply studied and analyzed. The new characteristics of DDR3 and the low power design technology are described in detail. Have a deep understanding of the working principle and working process of DDR3. 2. The structure of DDR3 memory controller is divided into two parts: transport layer and physical layer. The modules in the two parts are designed by Verilog. Modelsim-Altera is used to simulate the overall design of the controller. 3. The FPGA verification platform is built, the FPGA implementation of the DDR3 controller is introduced, the read and write function of the controller is verified and the self-detection model is tested. 4. In this paper, the memory control strategy is analyzed, and the method of memory access sequence scheduling is proposed to optimize the memory access delay.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP332

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相關(guān)期刊論文 前2條

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2 周昆正;基于FPGA的SDRAM控制器設(shè)計(jì)[J];現(xiàn)代電子技術(shù);2003年13期

本文編號(hào)：2247643