【摘要】：隨著多媒體業(yè)務(wù)和無線通信技術(shù)的快速發(fā)展,人們對多媒體應(yīng)用以及高速、可靠且無縫銜接的無線通信應(yīng)用的需求不斷膨脹,因此對面向多媒體廣播和無線通信技術(shù)的特定應(yīng)用多核處理器需求變得尤為重要。多核處理器的興起與發(fā)展,很大程度上是由于集成電路制造工藝技術(shù)的不斷進(jìn)步以及體系結(jié)構(gòu)設(shè)計(jì)的日益成熟。多媒體廣播和無線通信技術(shù)的信息處理,其核心是處理器。本課題針對面向未來多媒體廣播和無線通信算法的實(shí)際需求,研究新型的處理器體系結(jié)構(gòu)技術(shù),將處理器體系結(jié)構(gòu)的特點(diǎn)與特定應(yīng)用領(lǐng)域需求相結(jié)合,為未來的發(fā)展探索新的解決思路。本文針對多媒體廣播、無線通信以及信道編碼技術(shù)的應(yīng)用需求,提出并設(shè)計(jì)了一款面向特定應(yīng)用的多核處理器體系結(jié)構(gòu)。其主要工作如下:1、該多核處理器結(jié)構(gòu)在單芯片上基于2D-Mesh拓?fù)浣Y(jié)構(gòu)集成了15個(gè)處理器單元和一個(gè)共享存儲器節(jié)點(diǎn)單元。并且實(shí)現(xiàn)了基于共享存儲的核間通信方式。2、本文以MIPS指令為參考,設(shè)計(jì)并實(shí)現(xiàn)了一款兼容MIPS指令集的單核處理器,該處理器在Kintex?-7系列的XC7K70T-2fbg676硬件平臺上基于ISE14.6得出其最大工作頻率為91.533MHz,最小周期為10.925ns。為了實(shí)現(xiàn)其低開銷低延遲性,先對處理器各單元進(jìn)行了綜合實(shí)現(xiàn),最后對運(yùn)算部件進(jìn)行了實(shí)現(xiàn)與優(yōu)化。3、基于提前路由和推測技術(shù)提出一款僅需兩周期流水結(jié)構(gòu)的低開銷低延遲蟲孔虛通道路由器。在該路由器中加入了輸入端口請求屏蔽模塊并對兩種情況進(jìn)行了屏蔽。為了防止數(shù)據(jù)分組的丟失以及提高緩存(buffer)資源的利用率,提出了一種基于信用的流控(CBFC)機(jī)制。基于ISE14.6綜合后得出其最大工作頻率為297.983MHz,最小周期為3.356ns。為了驗(yàn)證路由器的低開銷低延遲性,設(shè)計(jì)并實(shí)現(xiàn)了其他幾種常用的路由器結(jié)構(gòu),通過對比得出該款路由器在延遲和資源開銷方面的優(yōu)勢。最后通過Splash-2應(yīng)用程序模擬真實(shí)應(yīng)用得到其平均延遲。4、為了兼容處理單元和低開銷低延遲路由器,實(shí)現(xiàn)了一款基于Wishbone總線的低開銷低延遲網(wǎng)絡(luò)接口,為了提升其低開銷低延遲性能,對可重構(gòu)單元異步FIFO進(jìn)行了設(shè)計(jì)與優(yōu)化。并在180nm工藝下使用DC綜合工具得出可重構(gòu)FIFO結(jié)構(gòu)的面積和功耗開銷。通過ISE14.6綜合出兩種網(wǎng)絡(luò)接口的開銷、頻率和延遲性能。5、為了論文的完備性,參照課題組其他成員的工作,基于特定應(yīng)用多核處理器對LDPC譯碼器、H.264解碼器和FFT譯碼器等方面進(jìn)行了映射方法的研究。
[Abstract]:With the rapid development of multimedia services and wireless communication technology, the demand for multimedia applications and high-speed, reliable and seamless wireless communication applications is expanding. Therefore, the demand for multi-core processors for multimedia broadcasting and wireless communication technologies becomes particularly important. To a large extent, it is due to the progress of IC manufacturing technology and the maturity of architecture design. The core of information processing in multimedia broadcasting and wireless communication technology is processor. In this paper, a multi-core processor architecture for specific applications is proposed and designed according to the application requirements of multimedia broadcasting, wireless communication and channel coding technology. This multi-core processor architecture integrates 15 processor units and a shared memory node unit on a single chip based on the 2D-Mesh topology. It also implements the inter-core communication mode based on shared memory. 2. This paper designs and implements a single-core processor compatible with MIPS instruction set, which is based on the MIPS instruction set. Based on ISE14.6, the XC7K70T-2fbg676 hardware platform of series?-7 has a maximum operating frequency of 91.533 MHz and a minimum cycle of 10.925 ns. In order to realize the low overhead and low latency, the processor units are synthetically implemented, and the computing units are optimized. 3. Based on the advanced routing and inference technology, a new one is proposed, which is only based on the advanced routing and inference technology. A low-overhead and low-latency wormhole virtual channel router with two-cycle pipeline architecture is proposed. Input port request shielding module is added to the router and two cases are shielded. In order to prevent the loss of data packets and improve the utilization of buffer resources, a credit-based flow control (CBFC) mechanism is proposed. In order to verify the low overhead and low latency of the router, several other commonly used router structures are designed and implemented, and the advantages of the router in delay and resource overhead are obtained by comparing. Finally, the real application is simulated by Splash-2 application program. The average delay is obtained. 4. In order to be compatible with processing units and low-overhead low-delay routers, a low-overhead and low-latency network interface based on Wishbone bus is implemented. In order to improve its low-overhead and low-latency performance, the reconfigurable unit asynchronous FIFO is designed and optimized, and the reconfigurable FIF is obtained by DC synthesis tool in 180 nm process. The overhead, frequency and delay performance of the two network interfaces are synthesized by ISE14.6. For the completeness of the paper and the work of other members of the research group, the mapping methods of LDPC decoder, H.264 decoder and FFT decoder are studied based on the special application multicore processor.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TP332
，

本文編號：2233820