【摘要】：隨著大規(guī)模集成電路、FPGA技術(shù)和計算機(jī)的快速發(fā)展，測試儀器的模塊化設(shè)計已經(jīng)成為了一種趨勢。為了滿足不同的測試需求，利用同一硬件平臺完成多個儀器的測試功能日益成為了測試數(shù)字化儀系統(tǒng)的研究熱點(diǎn)，其中功能模塊化、接口控制功能多樣化、高速率大容量采樣數(shù)據(jù)存儲是實(shí)現(xiàn)系統(tǒng)功能的關(guān)鍵。 基于FPGA技術(shù)的FMC（FPGA Mezzanine Card）接口，借助于FPGA的規(guī)模及性能的快速提高，在實(shí)時采樣系統(tǒng)的硬件擴(kuò)展應(yīng)用中，，已成為主流發(fā)展方向之一。但與ASIC相比，F(xiàn)PGA本身的安全性比較差。基于SRAM工藝的FPGA配置數(shù)據(jù)很容易被非法竊取，這將對設(shè)計者造成極大的經(jīng)濟(jì)損失。因此，保護(hù)FPGA設(shè)計的知識產(chǎn)權(quán)問題日趨嚴(yán)峻。 論文針對FMC實(shí)時采樣系統(tǒng)的特點(diǎn)和應(yīng)用需求，設(shè)計了具有加密功能的接口控制邏輯和帶靈活觸發(fā)機(jī)制的高速采樣存儲邏輯。FMC采集模塊通用載板的接口控制邏輯部分完成加密識別技術(shù)設(shè)計與高速數(shù)據(jù)流的接收和處理；而數(shù)據(jù)存儲邏輯部分實(shí)現(xiàn)基于DDR3SDRAM IP Core的采樣存儲控制。本文首先完成了一種基于SHA-1算法的加密認(rèn)證方式，以達(dá)到保護(hù)FPGA邏輯設(shè)計的目的；接著設(shè)計完成了基于DDR3SDRAM技術(shù)的高速采樣存儲控制器，它以提高采樣系統(tǒng)信號的捕獲和定時分辨能力為目標(biāo)，凸顯高速實(shí)時采樣系統(tǒng)中高速率、大容量以及快速觸發(fā)等特征；文中最后對設(shè)計內(nèi)容進(jìn)行了驗證，并給出了接口控制邏輯和高速采樣存儲控制器運(yùn)用于FMC數(shù)據(jù)采集模塊（FMC5212、FMC4214）的全性能測試結(jié)果。高速采樣存儲控制器能夠?qū)λ钠珼DR3SDRAM進(jìn)行并行觸發(fā)存儲，完全滿足系統(tǒng)最高采樣速率的存儲要求。加密認(rèn)證功能有效保護(hù)FPGA邏輯設(shè)計的知識產(chǎn)權(quán)，具有很好的推廣意義，最終將代碼打包以邏輯產(chǎn)品的形式發(fā)布。
[Abstract]:With the rapid development of large scale integrated circuit (LSI) FPGA technology and computer, modular design of test instruments has become a trend. In order to meet the different testing requirements, using the same hardware platform to complete the testing function of multiple instruments has become the research hotspot of the test digitizer system day by day, in which the function modularization, the interface control function is diversified, High speed and large capacity data storage is the key to realize the function of the system. The FMC (FPGA Mezzanine Card) interface based on FPGA technology, with the help of the rapid improvement of the scale and performance of FPGA, has become one of the mainstream development directions in the hardware extension application of real-time sampling system. But compared with ASIC, the security of ASIC itself is poor. FPGA configuration data based on SRAM process is easy to be stolen illegally, which will cause great economic loss to designers. Therefore, the protection of intellectual property rights of FPGA design is becoming more and more serious. This paper aims at the characteristics and application requirements of FMC real-time sampling system. The interface control logic with encryption function and high-speed sampling storage logic with flexible trigger mechanism. FMC acquisition module. The interface control logic of the universal carrier board completes the design of encryption identification technology and the reception and processing of high speed data flow. The data storage logic part realizes the sampling storage control based on DDR3SDRAM IP Core. In this paper, a encryption authentication method based on SHA-1 algorithm is first implemented to protect FPGA logic design, and then a high-speed sampling storage controller based on DDR3SDRAM technology is designed. It aims at improving the signal acquisition and timing resolution of the sampling system, and highlights the characteristics of high speed, large capacity and fast trigger in the high speed real-time sampling system. The full performance test results of interface control logic and high speed sampling memory controller applied to FMC data acquisition module (FMC5212,FMC4214) are also given. The high-speed sampling memory controller can trigger the memory of four pieces of DDR3SDRAM in parallel, which fully meets the storage requirement of the highest sampling rate of the system. The encryption authentication function effectively protects the intellectual property of FPGA logic design, and has good promotion significance. Finally, the code is packaged and released in the form of logic products.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP334.7;TP333

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