微處理器溫度感知的任務(wù)調(diào)度算法研究
發(fā)布時(shí)間：2018-09-07 06:46
【摘要】：隨著集成電路特征尺寸的不斷縮小以及集成度的不斷提高，處理器的功耗密度和溫度持續(xù)上升。過高的溫度不僅降低了芯片的可靠性，同時(shí)也對(duì)處理器的性能產(chǎn)生了很大的影響，溫度問題已經(jīng)成為限制微處理器持續(xù)發(fā)展的重要因素。而一些新興的技術(shù)（如單芯片多處理器、3D堆疊技術(shù)等）則進(jìn)一步增加了芯片的功耗密度，從而使得溫度問題變得更加嚴(yán)峻。 芯片的溫度在時(shí)間和空間上的巨大變化也給處理器的封裝和冷卻帶來了巨大挑戰(zhàn)，傳統(tǒng)的散熱方法已經(jīng)越來越不能滿足當(dāng)前高性能微處理器對(duì)散熱的要求。為了解決這一問題，目前普遍采用基于硬件的動(dòng)態(tài)熱管理技術(shù)（Hardware DynamicThermal Management，簡稱HW DTM）來限制處理器的溫度，即一旦硬件檢測到處理器的溫度達(dá)到某一預(yù)定的閾值，就啟動(dòng)相應(yīng)的溫度管理機(jī)制（比如降頻、降壓、斷電等）來降低處理器的溫度，保護(hù)處理器不被損壞。但是，HW DTM技術(shù)會(huì)增加程序的運(yùn)行時(shí)間，降低系統(tǒng)的吞吐率，最終降低處理器的性能。 本文的目標(biāo)就是要盡可能地消除不必要的HW DTM觸發(fā)事件，保護(hù)芯片的性能不受溫度管理機(jī)制的影響。本文系統(tǒng)地研究了基于溫度感知設(shè)計(jì)的一系列關(guān)鍵技術(shù)，針對(duì)已有工作的不足，提出了三種操作系統(tǒng)級(jí)的溫度感知任務(wù)調(diào)度技術(shù)來避免HW DTM。本文主要的工作和創(chuàng)新點(diǎn)包括： 第一，全面深入地分析了微處理器溫度感知設(shè)計(jì)技術(shù)，從不同層次、不同角度對(duì)現(xiàn)有的溫度感知設(shè)計(jì)技術(shù)進(jìn)行了總結(jié)，分析了這些技術(shù)的優(yōu)缺點(diǎn)。 第二，進(jìn)行溫度感知任務(wù)調(diào)度需要在線進(jìn)行功耗與溫度計(jì)算，本文總結(jié)了現(xiàn)有的功耗估算模型和溫度模型，對(duì)這些模型的特點(diǎn)進(jìn)行了分析，討論了功耗獲取和溫度計(jì)算的方法。 第三，，針對(duì)單核處理器，提出了一種貪婪調(diào)度算法GSA，在處理器溫度不超過閾值溫度的前提下讓熱的任務(wù)先運(yùn)行，充分利用處理器的時(shí)間“溫度余量”，將處理器較早提升到一個(gè)溫度較高的狀態(tài)，使處理器能更快地耗散熱量，從而減少DTM觸發(fā)次數(shù)，提升系統(tǒng)的性能。實(shí)驗(yàn)結(jié)果表明，GSA與基準(zhǔn)調(diào)度器相比，在低、中、高溫環(huán)境下的SPEC2K負(fù)載以及中溫環(huán)境下的非SPEC負(fù)載，DTM分別可以降低9.9%~82%（平均47.1%）、8.8%~73.8%（平均41.1%）、2.9%~58.7%（平均31.7%）和5.9%~45.5（平均31%），性能可以分別提升4.2%、5.2%、4.7%和3.7%；與隨機(jī)算法、優(yōu)先權(quán)算法、MinTemp+算法以及TreshHot算法相比，GSA均有不同程度的性能提升。 第四，針對(duì)2D CMP，提出了TSTB調(diào)度算法。CMP的自然分簇結(jié)構(gòu)為溫度管理提供了新的途徑，調(diào)度一個(gè)熱的任務(wù)到一個(gè)冷的核上比調(diào)度一個(gè)熱的任務(wù)到熱的核上，具有更低的峰值溫度。TSTB利用CMP在時(shí)間和空間上的溫度變化，通過改變冷熱任務(wù)的執(zhí)行順序來挖掘CMP每個(gè)核內(nèi)的時(shí)間“溫度余量”，并將冷熱任務(wù)安排到溫度適合的核上運(yùn)行來挖掘空間“溫度余量”，減少熱緊急事件，提升系統(tǒng)性能。實(shí)驗(yàn)結(jié)果表明，相比于基準(zhǔn)調(diào)度算法，TSTB算法使TET（ThermalEmergency Time）降低了8.3%~91.5%，平均降低了48.3%，使性能提升了2.47%~6.58%（平均4.62%）；TSTB相比于隨機(jī)調(diào)度算法、輪轉(zhuǎn)調(diào)度算法、平衡算法以及ThresHot算法等，均有不同程度的性能提升。 第五，針對(duì)3D CMP，提出了HTBS調(diào)度算法。分析了3D CMP的溫度特性，將垂直堆疊的核當(dāng)作一個(gè)核堆，讓任務(wù)的功耗在核堆之間進(jìn)行平衡，同時(shí)將熱的任務(wù)放在離熱沉近的核上運(yùn)行，以加速散熱。當(dāng)某個(gè)核出現(xiàn)過熱時(shí)，對(duì)核堆中功耗最密集的處理器核進(jìn)行DTM，使溫度迅速降低。實(shí)驗(yàn)結(jié)果表明，相比于基準(zhǔn)調(diào)度算法，HTBS算法使TET降低了8.4%~96.2%，平均降低了54.7%，獲得了5.99%的性能提升；HTBS算法相比于隨機(jī)調(diào)度、輪轉(zhuǎn)調(diào)度、核間溫度平衡調(diào)度以及堆間溫度平衡調(diào)度算法，均有不同程度的性能提升。
[Abstract]:With the shrinking of IC feature size and the continuous improvement of IC integration, the power density and temperature of processors continue to rise. Excessive temperature not only reduces the reliability of the chip, but also has a great impact on the performance of processors. Temperature problem has become an important factor limiting the sustainable development of microprocessors. Some emerging technologies, such as single-chip multiprocessor, 3D stacking technology, further increase the chip power density, thus making the temperature problem more serious.
The tremendous change of chip temperature in time and space also brings tremendous challenges to processor packaging and cooling. Traditional heat dissipation methods can not meet the current requirements of high performance microprocessors. Rmal management (HW DTM) is used to limit the processor's temperature, that is, once the hardware detects that the processor's temperature reaches a predetermined threshold, it starts the corresponding temperature management mechanism (such as frequency reduction, voltage reduction, power off, etc.) to reduce the processor's temperature and protect the processor from damage. However, HW DTM technology will increase the running time of the program. It reduces the throughput of the system and ultimately reduces the performance of the processor.
The goal of this paper is to eliminate unnecessary HW DTM trigger events as much as possible and to protect the performance of the chip from the influence of temperature management mechanism. Free HW DTM.. The main work and innovations in this paper include:
Firstly, the temperature sensing Design Technology of microprocessor is analyzed comprehensively and thoroughly. The existing temperature sensing design technology is summarized from different levels and angles, and the advantages and disadvantages of these technologies are analyzed.
Secondly, on-line power consumption and temperature calculation are needed for temperature-aware task scheduling. This paper summarizes the existing power estimation models and temperature models, analyzes the characteristics of these models, and discusses the methods of power consumption acquisition and temperature calculation.
Thirdly, a greedy scheduling algorithm GSA is proposed for single-core processors, which makes hot tasks run first when the processor temperature does not exceed the threshold temperature, and makes full use of the processor's time "temperature margin" to raise the processor to a higher temperature state earlier so that the processor can consume heat more quickly, thereby reducing DTM. The experimental results show that compared with the benchmark scheduler, GSA can reduce SPC2K load in low, medium, high temperature environment and non-SPEC load in medium temperature environment by 9.9% ~ 82% (average 47.1%), 8.8% ~ 73.8% (average 41.1%), 2.9% ~ 58.7% (average 31.7%) and 5.9% ~ 45.5% (average 31%) respectively. 4.2%, 5.2%, 4.7% and 3.7%. Compared with random algorithm, priority algorithm, MinTemp + algorithm and TreshHot algorithm, GSA has different performance improvements.
Fourthly, a TSTB scheduling algorithm is proposed for 2D CMP. The natural clustering structure of CMP provides a new way for temperature management, dispatching a hot task to a cold core has a lower peak temperature than dispatching a hot task to a hot core. TSTB uses the temperature variation of CMP in time and space to change the cold and hot tasks. The execution sequence is used to mine the time "temperature margin" in each core of CMP, and the cold and hot tasks are arranged to run on the core with suitable temperature to mine the space "temperature margin" to reduce thermal emergencies and improve system performance. The experimental results show that compared with the benchmark scheduling algorithm, the TSTB algorithm reduces the TET (Thermal Emergency Time) by 8.3%~91%. 5%, reduced by 48.3% on average, and improved the performance by 2.47%~6.58% (average 4.62%). Compared with random scheduling algorithm, rotation scheduling algorithm, balance algorithm and ThresHot algorithm, TSTB has improved the performance to varying degrees.
Fifthly, an HTBS scheduling algorithm is proposed for 3D CMP. The temperature characteristics of 3D CMP are analyzed. Vertical stacked cores are regarded as a nuclear reactor to balance the power consumption of the tasks between the nuclear reactors, and the hot tasks are placed on the cores near the heat sink to speed up the heat dissipation. The experimental results show that the HTBS algorithm reduces TET by 8.4%~96.2% and decreases TET by 54.7% compared with the benchmark scheduling algorithm, and achieves 5.99% performance improvement. Performance improvement.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：博士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP332
本文編號(hào)：2227504
[Abstract]:With the shrinking of IC feature size and the continuous improvement of IC integration, the power density and temperature of processors continue to rise. Excessive temperature not only reduces the reliability of the chip, but also has a great impact on the performance of processors. Temperature problem has become an important factor limiting the sustainable development of microprocessors. Some emerging technologies, such as single-chip multiprocessor, 3D stacking technology, further increase the chip power density, thus making the temperature problem more serious.
The tremendous change of chip temperature in time and space also brings tremendous challenges to processor packaging and cooling. Traditional heat dissipation methods can not meet the current requirements of high performance microprocessors. Rmal management (HW DTM) is used to limit the processor's temperature, that is, once the hardware detects that the processor's temperature reaches a predetermined threshold, it starts the corresponding temperature management mechanism (such as frequency reduction, voltage reduction, power off, etc.) to reduce the processor's temperature and protect the processor from damage. However, HW DTM technology will increase the running time of the program. It reduces the throughput of the system and ultimately reduces the performance of the processor.
The goal of this paper is to eliminate unnecessary HW DTM trigger events as much as possible and to protect the performance of the chip from the influence of temperature management mechanism. Free HW DTM.. The main work and innovations in this paper include:
Firstly, the temperature sensing Design Technology of microprocessor is analyzed comprehensively and thoroughly. The existing temperature sensing design technology is summarized from different levels and angles, and the advantages and disadvantages of these technologies are analyzed.
Secondly, on-line power consumption and temperature calculation are needed for temperature-aware task scheduling. This paper summarizes the existing power estimation models and temperature models, analyzes the characteristics of these models, and discusses the methods of power consumption acquisition and temperature calculation.
Thirdly, a greedy scheduling algorithm GSA is proposed for single-core processors, which makes hot tasks run first when the processor temperature does not exceed the threshold temperature, and makes full use of the processor's time "temperature margin" to raise the processor to a higher temperature state earlier so that the processor can consume heat more quickly, thereby reducing DTM. The experimental results show that compared with the benchmark scheduler, GSA can reduce SPC2K load in low, medium, high temperature environment and non-SPEC load in medium temperature environment by 9.9% ~ 82% (average 47.1%), 8.8% ~ 73.8% (average 41.1%), 2.9% ~ 58.7% (average 31.7%) and 5.9% ~ 45.5% (average 31%) respectively. 4.2%, 5.2%, 4.7% and 3.7%. Compared with random algorithm, priority algorithm, MinTemp + algorithm and TreshHot algorithm, GSA has different performance improvements.
Fourthly, a TSTB scheduling algorithm is proposed for 2D CMP. The natural clustering structure of CMP provides a new way for temperature management, dispatching a hot task to a cold core has a lower peak temperature than dispatching a hot task to a hot core. TSTB uses the temperature variation of CMP in time and space to change the cold and hot tasks. The execution sequence is used to mine the time "temperature margin" in each core of CMP, and the cold and hot tasks are arranged to run on the core with suitable temperature to mine the space "temperature margin" to reduce thermal emergencies and improve system performance. The experimental results show that compared with the benchmark scheduling algorithm, the TSTB algorithm reduces the TET (Thermal Emergency Time) by 8.3%~91%. 5%, reduced by 48.3% on average, and improved the performance by 2.47%~6.58% (average 4.62%). Compared with random scheduling algorithm, rotation scheduling algorithm, balance algorithm and ThresHot algorithm, TSTB has improved the performance to varying degrees.
Fifthly, an HTBS scheduling algorithm is proposed for 3D CMP. The temperature characteristics of 3D CMP are analyzed. Vertical stacked cores are regarded as a nuclear reactor to balance the power consumption of the tasks between the nuclear reactors, and the hot tasks are placed on the cores near the heat sink to speed up the heat dissipation. The experimental results show that the HTBS algorithm reduces TET by 8.4%~96.2% and decreases TET by 54.7% compared with the benchmark scheduling algorithm, and achieves 5.99% performance improvement. Performance improvement.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：博士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP332
【參考文獻(xiàn)】
相關(guān)期刊論文 前1條
1 梁穎;黃春躍;閻德勁;李天明;;基于熱疊加模型的疊層3D多芯片組件芯片熱布局優(yōu)化研究[J];電子學(xué)報(bào);2009年11期
本文編號(hào)：2227504
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