【摘要】：隨著信息技術(shù)的快速發(fā)展，人們對計(jì)算機(jī)外設(shè)的傳輸速度提出了更高的要求，，多種接口標(biāo)準(zhǔn)應(yīng)運(yùn)而生，包括USB、IEEE1394、FiberChannel、SSA、Ultra SCSI等。IEEE1394作為一種高速串行總線標(biāo)準(zhǔn)，不管是傳輸速度還是數(shù)據(jù)可靠性都具有很大優(yōu)勢。它不僅支持熱拔插，還具有等時(shí)傳輸和異步傳輸兩種通信方式，廣泛應(yīng)用于航空航天、數(shù)碼攝像機(jī)、高速外接硬盤、打印機(jī)等多種設(shè)備。 本文研究的物理層IP核是IEEE1394芯片的一個(gè)子模塊。它負(fù)責(zé)將數(shù)據(jù)從鏈路層發(fā)送到總線接口，以及將總線上接收的數(shù)據(jù)轉(zhuǎn)發(fā)給鏈路層。本次設(shè)計(jì)的物理層IP核符合IEEE1394a協(xié)議，它實(shí)現(xiàn)了物理層的基本功能，傳輸速度最高達(dá)到400Mbps，可以單獨(dú)流片或同其他協(xié)議層做成SOC產(chǎn)品。對IEEE1394芯片的研究工作具有一定的參考意義和實(shí)用價(jià)值。 本文首先分析了IEEE1394協(xié)議的基本內(nèi)容，重點(diǎn)闡述了協(xié)議中有關(guān)物理層的仲裁機(jī)制和通信原理。然后根據(jù)功能要求，提出了物理層IP核的系統(tǒng)級解決方案，并完成了每個(gè)子模塊的設(shè)計(jì)工作，同時(shí)制定了每個(gè)子模塊的外部接口信號以及內(nèi)部狀態(tài)機(jī)描述。整個(gè)過程采用自上而下的設(shè)計(jì)思路。為了保證設(shè)計(jì)結(jié)果的正確性和可靠性，最后搭建了系統(tǒng)級驗(yàn)證平臺(tái)，制定了詳細(xì)驗(yàn)證方案，并用modelsim6.5仿真工具對設(shè)計(jì)結(jié)果進(jìn)行了功能仿真，仿真結(jié)果表明此次IP核設(shè)計(jì)的功能和時(shí)序均滿足協(xié)議要求。
[Abstract]:With the rapid development of information technology, people put forward higher requirements for the transmission speed of computer peripherals. A variety of interface standards emerge as the times require, including USB,IEEE1394,FiberChannel,SSA,Ultra SCSI, etc., as a high-speed serial bus standard. Both transmission speed and data reliability have great advantages. It not only supports hot plug, but also has two communication modes: isochronous transmission and asynchronous transmission. It is widely used in aerospace, digital camera, high-speed external hard disk, printer and other devices. The physical layer IP core studied in this paper is a sub-module of IEEE1394 chip. It is responsible for transmitting data from the link layer to the bus interface and forwarding the data received on the bus to the link layer. The design of the physical layer IP core accords with the IEEE1394a protocol, it realizes the basic functions of the physical layer, the transmission speed is up to 400 Mbps. it can be made into SOC products on a single stream sheet or with other protocol layers. It has certain reference significance and practical value to the research work of IEEE1394 chip. In this paper, the basic content of IEEE1394 protocol is analyzed, and the arbitration mechanism and communication principle of the physical layer in the protocol are expounded. Then, according to the functional requirements, the system-level solution of the physical layer IP core is proposed, and the design of each sub-module is completed. At the same time, the external interface signals of each sub-module and the description of the internal state machine are worked out. The whole process adopts a top-down design idea. In order to ensure the correctness and reliability of the design results, a system-level verification platform is built, a detailed verification scheme is established, and the design results are simulated with modelsim6.5 simulation tools. The simulation results show that the function and timing of the IP core design meet the requirements of the protocol.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP336;TN402

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