【摘要】：提出了一種基于FPGA的進(jìn)位存儲(chǔ)的大數(shù)乘法器的改進(jìn)算法,該算法采用串并混合結(jié)構(gòu)可以在一個(gè)時(shí)鐘內(nèi)完成多次迭代計(jì)算,減少了完成一次運(yùn)算的時(shí)鐘數(shù),因此有效地提高了大數(shù)乘法器的速度。最后硬件結(jié)構(gòu)設(shè)計(jì)在Altera Stratix Ⅱ EP2S90F1508C3上實(shí)現(xiàn),給出了192位、256位以及384位的乘法器性能分析,其中,192位可達(dá)到0.18μs,256位達(dá)到0.27μs,384位達(dá)到0.59μs,速度上都提高了3.5倍左右。
[Abstract]:In this paper, an improved algorithm of carry store large number multiplier based on FPGA is proposed. This algorithm can perform multiple iterations in a single clock by using a series-parallel hybrid structure, thus reducing the number of clocks to complete a single operation. Therefore, the speed of the multiplier is improved effectively. Finally, the hardware structure is implemented on Altera Stratix 鈪，

本文編號(hào)：2211521