【摘要】：結(jié)合信息安全的需求以及SoC技術(shù)的發(fā)展,設(shè)計了一種基于AES加解密算法的AXI總線加密IP,達(dá)到從CPU到slave的整個數(shù)據(jù)通路的加解密目的,實(shí)現(xiàn)SoC內(nèi)部的端到端加密.其中通過內(nèi)置多個FIFO,分別在讀寫通道緩存CPU發(fā)出的AXI Burst傳輸,保證CPU發(fā)出的總線傳輸可以被順序的加解密處理.在AES算法實(shí)現(xiàn)方面,完成了ECB,CTR兩種便于并行處理的加密模式.在讀寫通道分別加入AES實(shí)現(xiàn)模塊,保證加解密操作的并行處理.同時構(gòu)建結(jié)構(gòu)化的UVM驗(yàn)證平臺,結(jié)合APB和AXI的VIP來實(shí)現(xiàn)對該IP的隨機(jī)約束和覆蓋率分析,最終通過Synopsys的VCS仿真工具完成功能驗(yàn)證.
[Abstract]:Combined with the requirement of information security and the development of SoC technology, a AXI bus encryption IP, based on AES encryption and decryption algorithm is designed to achieve the purpose of encrypting and decrypting the whole data path from CPU to slave, and to realize end-to-end encryption in SoC. The AXI Burst transmission sent by CPU is cached in the read and write channel by built-in FIFO, which ensures that the bus transmission emitted by CPU can be sequentially encrypted and decrypted. In the aspect of AES algorithm implementation, two encryption modes of ECB,CTR are completed which are convenient for parallel processing. AES modules are added to read and write channels to ensure parallel processing of encryption and decryption operations. At the same time, the structured UVM verification platform is constructed, and the random constraint and coverage analysis of the IP is realized by combining APB and AXI VIP. Finally, the function verification is completed by the VCS simulation tool of Synopsys.
【作者單位】： 杭州電子科技大學(xué)自動化學(xué)院;
【分類號】：TN918.4;TP336
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本文編號：2203825