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基于FPGA的高速寬帶數(shù)據(jù)處理

發(fā)布時間:2018-08-19 05:55
【摘要】:隨著信息產(chǎn)業(yè)的快速發(fā)展,通信、電子、多媒體等行業(yè)對數(shù)據(jù)傳輸?shù)乃俣纫约皫挼男枨蟛粩嘣黾。如何實現(xiàn)可靠、高速的寬帶數(shù)據(jù)傳輸已經(jīng)成為一個熱門課題;谝陨媳尘,本課題設(shè)計了一款基于PCI Express總線的高速寬帶數(shù)據(jù)傳輸與處理方案,從而實現(xiàn)了數(shù)據(jù)實時、高速地從計算機傳入目標板并進行數(shù)據(jù)處理的過程,并且通過一系列實驗設(shè)計,對PCI Express總線性能進行驗證。 本課題簡述了PCI Express總線協(xié)議、總線架構(gòu)以及傳輸方式。在此基礎(chǔ)上,從邏輯設(shè)計、軟件設(shè)計兩個方面詳細闡述了一種實現(xiàn)高速寬帶數(shù)據(jù)傳輸與處理的方案。在邏輯方面,重點闡述了基于Altera Cyclone IV GX系列開發(fā)板的PCI Express,總線設(shè)計方案,詳細描述了利用Altera Hard IP實現(xiàn)PCI Express傳輸層、數(shù)據(jù)鏈路層、物理層的設(shè)計過程。PCI Express應(yīng)用層設(shè)計是本文的技術(shù)重點。本課題在已有Altera Hard IP設(shè)計基礎(chǔ)上,在PCI Express應(yīng)用層實現(xiàn)了FFT設(shè)計并且將已有鏈路進行劃分,逐步測試了PCI Express鏈路的性能,從而實現(xiàn)了高速寬帶數(shù)據(jù)的傳輸與處理。軟件部分,本課題采用功能強大、開發(fā)周期較短的WinDriver進行PCI Express驅(qū)動程序設(shè)計,主要闡述了利用WinDriver開發(fā)設(shè)備驅(qū)動的優(yōu)勢與開發(fā)設(shè)計流程,針對關(guān)鍵API函數(shù)進行了詳細描述。在此基礎(chǔ)上,本課題給出了利用MSVisual C++6.0開發(fā)環(huán)境設(shè)計PC端應(yīng)用程序方案。在本論文結(jié)論部分給出了總體設(shè)計所達到的傳輸性能以及各個設(shè)計的測試結(jié)果。 本文提出的設(shè)計通過模塊級和系統(tǒng)級的功能仿真以及性能測試,能夠穩(wěn)定的運行。結(jié)果表明,本課題設(shè)計可以滿足高速寬帶數(shù)據(jù)傳輸以及處理的要求。
[Abstract]:With the rapid development of information industry, communication, electronics, multimedia and other industries of data transmission speed and bandwidth requirements are increasing. How to achieve reliable, high-speed broadband data transmission has become a hot topic. Based on the above background, this paper designs a high-speed broadband data transmission and processing scheme based on PCI Express bus, which realizes the process of real-time data transmission and high-speed data processing from the computer to the target board. And through a series of experimental design, the performance of PCI Express bus is verified. This paper describes the PCI Express bus protocol, bus architecture and transmission mode. On this basis, a scheme for high-speed broadband data transmission and processing is described in detail from two aspects: logic design and software design. In the aspect of logic, the design scheme of PCI express and bus based on Altera Cyclone IV GX series development board is expounded, and the realization of PCI Express transport layer and data link layer by using Altera Hard IP is described in detail. The design process of physical layer. PCI Express application layer design is the focus of this paper. Based on the existing Altera Hard IP design, the FFT design is implemented in the PCI Express application layer and the existing links are partitioned. The performance of the PCI Express link is tested step by step, thus the transmission and processing of high-speed broadband data are realized. In the software part, the WinDriver with powerful function and short development period is used to design the PCI Express driver. The advantages and the design flow of using WinDriver to develop the device driver are mainly expounded, and the key API functions are described in detail. On the basis of this, the project of designing PC-side application program using MSVisual C 6. 0 development environment is given. In the last part of the thesis, the transmission performance of the whole design and the test results of each design are given. The design presented in this paper can run stably through function simulation and performance test at module and system level. The results show that the design can meet the requirements of high-speed broadband data transmission and processing.
【學位授予單位】:北京郵電大學
【學位級別】:碩士
【學位授予年份】:2013
【分類號】:TP336;TN791

【參考文獻】

相關(guān)期刊論文 前10條

1 魏鵬;羅武勝;杜列波;;PCI Express總線及其應(yīng)用設(shè)計研究[J];電測與儀表;2007年02期

2 焦文U,

本文編號:2190823


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