【摘要】：在計(jì)算機(jī)硬件電路設(shè)計(jì)中，內(nèi)存芯片與主控芯片的互連設(shè)計(jì)是整個(gè)計(jì)算機(jī)系統(tǒng)設(shè)計(jì)的關(guān)鍵。系統(tǒng)能否穩(wěn)定運(yùn)行，與內(nèi)存模組(簡稱內(nèi)存，Memory Module)密不可分。計(jì)算機(jī)、手機(jī)和網(wǎng)絡(luò)通信的快速發(fā)展是內(nèi)存發(fā)展的后臺(tái)推動(dòng)力，尤其是在大數(shù)據(jù)，云處理等應(yīng)用背景下，需要收集大量數(shù)據(jù)并進(jìn)行實(shí)時(shí)處理，或者存儲(chǔ)后再進(jìn)行分析處理。內(nèi)存的工作頻率、工作電壓及總線帶寬等技術(shù)指標(biāo)快速發(fā)展，目的在于提高內(nèi)存的帶寬及效率，滿足CPU不斷攀升的帶寬及性能要求，避免其成為高速運(yùn)算的瓶頸。論文針對(duì)DDR3內(nèi)存模組的PCB高速電路設(shè)計(jì)不僅是國內(nèi)外研究的熱點(diǎn)，而且可為將來DDR4內(nèi)存產(chǎn)品的設(shè)計(jì)奠定堅(jiān)實(shí)基礎(chǔ)。 本文首先分析了信號(hào)完整性和電源完整性基礎(chǔ)理論，并將其運(yùn)用于指導(dǎo)后期元器件布局、布線、拓?fù)浣Y(jié)構(gòu)、層疊結(jié)構(gòu)、阻抗控制和電源分配。其次，對(duì)動(dòng)態(tài)隨機(jī)存儲(chǔ)器(DRAM)的基本結(jié)構(gòu)、工作原理、電氣特性及時(shí)序進(jìn)行了分析，根據(jù)設(shè)計(jì)要求確定核心器件選型，完成電路原理圖設(shè)計(jì)，，借助Hspice/Hyperlynx前仿真工具分析DDR3地址/控制/命令/時(shí)鐘/數(shù)據(jù)信號(hào)，信號(hào)時(shí)序及完整性良好。然后提出DDR3高速電路設(shè)計(jì)及布線規(guī)則，利用規(guī)則驅(qū)動(dòng)PCB布局布線完成，后仿真驗(yàn)證PCB符合設(shè)計(jì)規(guī)范。最后，生產(chǎn)樣品并完成整板測(cè)試。電源測(cè)試、讀寫測(cè)試、RMT測(cè)試，高速示波器SI測(cè)試結(jié)果良好，均符合JEDEC設(shè)計(jì)規(guī)范。
[Abstract]:In the design of computer hardware circuit, the interconnect design of memory chip and main control chip is the key of the whole computer system design. Whether the system can run stably is closely related to memory Module. The rapid development of computer, mobile phone and network communication is the background driving force of memory development, especially in the background of big data, cloud processing and other applications, it needs to collect a large amount of data and process it in real time, or analyze and process it after storage. The working frequency, working voltage and bus bandwidth of memory are developing rapidly. The purpose is to improve the bandwidth and efficiency of memory, to meet the increasing bandwidth and performance requirements of CPU, and to avoid the bottleneck of high speed operation. In this paper, the design of PCB high-speed circuit for DDR3 memory module is not only a hot topic at home and abroad, but also a solid foundation for the design of DDR4 memory products in the future. In this paper, the basic theory of signal integrity and power integrity is analyzed, and applied to guide the late component layout, wiring, topology, stack structure, impedance control and power allocation. Secondly, the basic structure, working principle, electrical characteristics and timing of dynamic random access memory (DRAM) are analyzed. According to the design requirements, the selection of core devices is determined, and the circuit schematic design is completed. The DDR3 address / control / command / clock / data signal is analyzed by Hspice/Hyperlynx simulation tools, and the timing and integrity of the signal are good. Then the DDR3 high-speed circuit design and routing rules are proposed. The rules are used to drive the PCB layout and routing. The post-simulation verifies that PCB conforms to the design specification. Finally, the sample is produced and the whole board test is completed. Power test, read and write test, high speed oscilloscope SI test result is good, all accord with JEDEC design standard.
【學(xué)位授予單位】：蘇州大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TP333.1

【參考文獻(xiàn)】

相關(guān)期刊論文 前2條

1 李晉文;胡軍;曹躍勝;史林森;肖立權(quán);;DDR3時(shí)序分析與設(shè)計(jì)[J];計(jì)算機(jī)科學(xué);2012年04期

2 王繼斌;;DDR3存儲(chǔ)器前沿技術(shù)分析[J];科技信息;2009年34期

本文編號(hào)：2190777