【摘要】：當(dāng)今科技發(fā)展日新月異,其發(fā)展速度之快令人難以置信,特別是在通訊領(lǐng)域,對(duì)大量數(shù)據(jù)傳輸?shù)母咚俣�、大帶寬和可靠性提出了更高的要求。新型聲納系統(tǒng)不光在軍用領(lǐng)域,包括民用探測(cè)方面都具有及其重要的價(jià)值和作用。而一套完整的聲納系統(tǒng)包括前端采集、信號(hào)處理、顯示控制、存儲(chǔ)回放等諸多部分,而如何為聲納系統(tǒng)提供高速、可靠的數(shù)據(jù)傳輸和系統(tǒng)互聯(lián)是其研究的重點(diǎn)。 本文主要研究基于CPCI架構(gòu)的嵌入式數(shù)據(jù)傳輸系統(tǒng)設(shè)計(jì)。根據(jù)聲納系統(tǒng)對(duì)數(shù)據(jù)傳輸?shù)母呖煽啃院蛷?qiáng)實(shí)時(shí)性的要求,以及信號(hào)處理平臺(tái)的拓?fù)浣Y(jié)構(gòu)對(duì)傳輸、互聯(lián)的要求,存儲(chǔ)回放設(shè)備和顯示控制設(shè)備對(duì)信號(hào)再生性能的要求,有針對(duì)性的設(shè)計(jì)實(shí)現(xiàn)本數(shù)據(jù)傳輸系統(tǒng)。 本論文在的設(shè)計(jì)實(shí)現(xiàn)在一塊標(biāo)準(zhǔn)加固CPCI架構(gòu)的6U大小的板卡,整篇論文在基于對(duì)核心技術(shù)的研究和總結(jié)的基礎(chǔ)之上,采用模塊的設(shè)計(jì)方法,在論文中著重闡述整板的硬件設(shè)計(jì),并且介紹支撐的軟件平臺(tái)、測(cè)試程序和驅(qū)動(dòng)程序。本設(shè)計(jì)采用基于DSP+FPGA的處理器架構(gòu),應(yīng)用高速串行傳輸技術(shù)和控制協(xié)議,物理通道上使用光纖傳輸技術(shù),并且結(jié)合TS201芯片高速LINK通道和數(shù)字信號(hào)處理平臺(tái)的拓?fù)浣Y(jié)構(gòu),設(shè)計(jì)實(shí)現(xiàn)高速穩(wěn)定數(shù)據(jù)傳輸和互聯(lián)結(jié)構(gòu)。 本論文在FPGA芯片的選擇上,立足Xilinx公司的Virtex5系列的FPGA芯片,采用模塊化的設(shè)計(jì)思想,分別實(shí)現(xiàn)PCI總線到DSP總線的轉(zhuǎn)換橋邏輯設(shè)計(jì)和光纖通道控制協(xié)議的邏輯設(shè)計(jì)。在DSP芯片的選擇上,則采用ADI公司的TS201DSP芯片,作為核心的數(shù)據(jù)處理芯片,.從而實(shí)現(xiàn)單板的數(shù)據(jù)校驗(yàn)和算法實(shí)現(xiàn)。本設(shè)計(jì)中集成了兩路不同帶寬的光纖通道,并且采用冗余設(shè)計(jì)的思想,每種帶寬的光纖通道都有一路熱備份,充分保證可靠性。 本論文在完成硬件和軟件設(shè)計(jì)之后,搭建完整的硬件測(cè)試平臺(tái)對(duì)設(shè)計(jì)指標(biāo)進(jìn)行測(cè)試,并且給出的測(cè)試結(jié)果,測(cè)試數(shù)據(jù)符合設(shè)計(jì)的最初設(shè)計(jì)指標(biāo)。利用模塊化的設(shè)計(jì)思想完成基于CPCI以DSP+FPGA為處理架構(gòu)的光纖傳輸硬件板卡,相比于傳統(tǒng)基于CPCI數(shù)據(jù)傳輸系統(tǒng)的硬件板卡：?jiǎn)伟鍖?shí)現(xiàn)最小系統(tǒng)；單板具備多種帶寬的光纖數(shù)據(jù)通道；硬件設(shè)計(jì)實(shí)現(xiàn)模塊化。本應(yīng)用設(shè)計(jì)的最終實(shí)現(xiàn),在保證了聲納系統(tǒng)數(shù)據(jù)互聯(lián)可靠性的前提下,大大提高了傳輸效率,具備很高的工程應(yīng)用價(jià)值。 本文共有圖41幅,表3個(gè),參考文獻(xiàn)32篇
[Abstract]:With the rapid development of science and technology, the speed of development is incredible, especially in the field of communication, which puts forward higher requirements for the high speed, large bandwidth and reliability of a large amount of data transmission. The new sonar system not only plays an important role in military field, but also in civil detection. A complete sonar system includes front-end acquisition, signal processing, display control, storage and playback, and how to provide high-speed, reliable data transmission and system interconnection for the sonar system is the focus of its research. This paper mainly studies the design of embedded data transmission system based on CPCI architecture. According to the requirements of the sonar system for high reliability and strong real-time performance of data transmission, as well as the requirements of the topological structure of the signal processing platform for transmission and interconnection, the requirements of the storage and playback equipment and the display control equipment for the signal regeneration performance, Targeted design and implementation of the data transmission system. The design of this paper is realized in a standard CPCI frame of 6U size card. Based on the research and summary of the core technology, this paper uses the design method of module, and emphasizes the hardware design of the whole board in this paper. The software platform, test program and driver are also introduced. This design adopts processor architecture based on DSP FPGA, applies high-speed serial transmission technology and control protocol, uses optical fiber transmission technology on physical channel, and combines the topology of TS201 chip high-speed LINK channel and digital signal processing platform. Design and implementation of high-speed and stable data transmission and interconnection structure. On the choice of FPGA chip, based on the FPGA chip of Virtex5 series of Xilinx Company, this paper adopts the modular design idea to realize the logic design of the conversion bridge from PCI bus to DSP bus and the logic design of optical fiber channel control protocol respectively. In the selection of DSP chip, ADI TS201DSP chip is used as the core data processing chip. Thus, the data checksum algorithm of single board is realized. In this design, two optical fiber channels with different bandwidth are integrated, and the redundant design is adopted. Each bandwidth fiber channel has a hot backup, which fully ensures the reliability. After the completion of hardware and software design, this paper builds a complete hardware test platform to test the design indicators, and gives the test results, the test data accord with the original design indicators. Using the modularization design idea, the optical fiber transmission hardware card based on CPCI and DSP FPGA is completed. Compared with the traditional hardware card based on CPCI data transmission system, the single board realizes the minimum system; Single board has a variety of bandwidth optical fiber data channel; hardware design to achieve modularization. The final implementation of this application design, on the premise of guaranteeing the reliability of sonar system data interconnection, greatly improves the transmission efficiency and has high engineering application value. There are 41 figures, 3 tables and 32 references in this paper.
【學(xué)位授予單位】：北京交通大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TN919.3;TP368.1

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