【摘要】：隨著嵌入式應(yīng)用的不斷多變、復(fù)雜化，傳統(tǒng)的通用處理器以及專用集成電路很難滿足高性能、高靈活性的需求。可重構(gòu)處理器因其較高的能效比、運算資源豐富、互連形式靈活而在嵌入式設(shè)計領(lǐng)域受到廣泛關(guān)注。 本文將算法分類為計算密集型、控制密集型、計算控制密集型，I/O密集型，數(shù)據(jù)密集型這五大類，并對當前主流的三種粗粒度和兩種多粒度可重構(gòu)處理器進行結(jié)構(gòu)建模的基礎(chǔ)上，分別進行了算法到可重構(gòu)結(jié)構(gòu)模型的映射。本文進而利用仿真結(jié)果從硬件利用率，計算時間，輸入、輸出帶寬，數(shù)據(jù)組織形式，，數(shù)據(jù)復(fù)用等五個方面對可重構(gòu)處理器的性能和算法的適應(yīng)性進行分析�；诜治鼋Y(jié)論以及現(xiàn)有的可重構(gòu)結(jié)構(gòu)模型提出一種可重構(gòu)陣列的設(shè)計結(jié)構(gòu)，從陣列單元，互連結(jié)構(gòu)，存儲機制，配置機制，流水線，控制機制等方面全面介紹陣列結(jié)構(gòu)。 本文對可重構(gòu)陣列采用Verilog HDL語言進行硬件建模，并通過仿真，在TSMC90nm工藝下綜合，時鐘頻率為100MHz，從算法映射結(jié)果的來看，與同類型可重構(gòu)處理器的映射結(jié)果相比，在完成性能差不多的情況下，硬件利用率更高，同時為可重構(gòu)處理器走向通用計算和相關(guān)的可重構(gòu)架構(gòu)設(shè)計提供了重要依據(jù)。
[Abstract]:With the increasing variety and complexity of embedded applications, it is difficult for traditional general-purpose processors and ASIC to meet the requirements of high performance and high flexibility. Reconfigurable processors have attracted wide attention in embedded design due to their high energy efficiency ratio, rich computing resources and flexible interconnection forms. In this paper, the algorithms are classified as computational intensive, control intensive, computational control intensive, I / O intensive and data intensive. Based on the structural modeling of three kinds of coarse-grained processors and two kinds of multi-granularity reconfigurable processors, The algorithm is mapped to the reconfigurable structure model. In this paper, the performance of the reconfigurable processor and the adaptability of the algorithm are analyzed from five aspects: hardware utilization, computing time, input, output bandwidth, data organization and data reuse. Based on the analysis results and the existing reconfigurable structure model, a design structure of reconfigurable array is proposed. The array structure is introduced from the aspects of array unit, interconnection structure, storage mechanism, configuration mechanism, pipeline, control mechanism and so on. In this paper, the Verilog HDL language is used to model the hardware of the reconfigurable array. The simulation results show that the clock frequency is 100 MHz under the TSMC90nm technology. From the point of view of the algorithm mapping results, compared with the mapping results of the same type of reconfigurable processors, In the case of similar performance, the hardware utilization is higher, and it provides an important basis for the reconfigurable processor to move towards general computing and related reconfigurable architecture design.
【學(xué)位授予單位】：上海交通大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP368.12

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相關(guān)碩士學(xué)位論文 前1條

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