【摘要】：隨著數(shù)字信號(hào)處理器（DSP）處理能力的不斷加強(qiáng)，總線技術(shù)從單總線到多總線的不斷進(jìn)步，實(shí)現(xiàn)數(shù)據(jù)的高速傳輸和多總線結(jié)構(gòu)控制成了現(xiàn)代DSP設(shè)計(jì)的關(guān)鍵技術(shù)之一。X-QDSP是我校自主研發(fā)的一款高性能DSP，該芯片擁有復(fù)雜的總線系統(tǒng)，內(nèi)部總線控制中心Switch Bus維護(hù)了8套讀寫總線，且與片上總線AXI完全不同。為解決具有AXI接口的SRIO IP核與系統(tǒng)總線之間的高速互聯(lián)，本文設(shè)計(jì)了一款128位的AXI總線橋接控制器，用于實(shí)現(xiàn)AXI與片內(nèi)不同總線協(xié)議之間的無(wú)縫對(duì)接。 基于多總線結(jié)構(gòu)控制的復(fù)雜性，，本文深入分析了QDSP中部件間的傳輸協(xié)議，設(shè)計(jì)了固定優(yōu)先級(jí)和令牌輪轉(zhuǎn)結(jié)合的總線仲裁機(jī)制，保證數(shù)據(jù)傳輸?shù)臅惩ā?為實(shí)現(xiàn)多樣化數(shù)據(jù)傳輸目的，設(shè)計(jì)了4個(gè)獨(dú)立并發(fā)的讀寫通道構(gòu)成的AXI總線橋接控制器，其中2個(gè)SRIO主機(jī)通道處理DSP內(nèi)核啟動(dòng)的數(shù)據(jù)傳輸，具有DMA功能的AXI總線橋接控制器SRIO主機(jī)通道完成數(shù)據(jù)傳輸?shù)暮笈_(tái)操作；2個(gè)SRIO從機(jī)通道處理SRIO部件啟動(dòng)的數(shù)據(jù)傳輸，該從機(jī)通道直接接收來(lái)自SRIO部件的傳輸請(qǐng)求，并將其轉(zhuǎn)化為Switch Bus總線上的傳輸命令。 根據(jù)各通道傳輸特點(diǎn)，采用高速緩沖結(jié)構(gòu)有效解決了數(shù)據(jù)的合并、拆分控制和地址不對(duì)齊傳輸?shù)燃夹g(shù)難點(diǎn)。采用狀態(tài)機(jī)集中控制方式實(shí)現(xiàn)了不同傳輸協(xié)議、不同位寬的總線之間的橋接互聯(lián)，保證數(shù)據(jù)傳輸?shù)母咝�。采用異步FIFO技術(shù)設(shè)計(jì)了深度為4的異步FIFO控制器，實(shí)現(xiàn)了SRIO部件與芯片系統(tǒng)總線的異步對(duì)接，解決了系統(tǒng)總線頻率和SRIO工作頻率不一致的問(wèn)題。 論文對(duì)橋接控制器進(jìn)行了充分的模塊級(jí)、部件級(jí)和系統(tǒng)級(jí)功能模擬驗(yàn)證，并統(tǒng)計(jì)了代碼覆蓋率。驗(yàn)證結(jié)果表明，該部件功能正確，滿足系統(tǒng)設(shè)計(jì)要求。 論文基于65nmCMOS工藝對(duì)橋接控制器進(jìn)行了邏輯綜合，并對(duì)設(shè)計(jì)進(jìn)行了結(jié)構(gòu)和時(shí)序優(yōu)化。綜合結(jié)果表明，在工藝最惡劣情況下，AXI總線橋接控制器工作頻率可以達(dá)到500MHz，達(dá)到了預(yù)期設(shè)計(jì)目標(biāo)。
[Abstract]:With the development of digital signal processor (DSP) processing ability, bus technology is developing from single bus to multi-bus. The realization of high-speed data transmission and multi-bus structure control has become one of the key technologies in modern DSP design. X-QDSP is a high-performance DSP developed by our university. The chip has a complex bus system. The internal bus control center (Switch Bus) maintains 8 sets of read and write buses, which are completely different from the on-chip bus (AXI). In order to solve the high speed interconnection between SRIO IP core with AXI interface and system bus, a 128-bit AXI bus bridge controller is designed to realize seamless docking between AXI and different bus protocols. Based on the complexity of multi-bus structure control, this paper deeply analyzes the transmission protocol between components in QDSP, designs a bus arbitration mechanism combining fixed priority and token rotation to ensure the smooth transmission of data. In order to achieve the purpose of diversified data transmission, a AXI bus bridge controller composed of four independent concurrent read and write channels is designed, in which two SRIO host channels handle data transmission initiated by the DSP kernel. The AXI bus bridging controller with DMA function, the SRIO host channel completes the background operation of data transmission, two SRIO slave channels handle the data transmission initiated by the SRIO component, and the slave channel directly receives the transmission request from the SRIO part. It is transformed into the transmission command on the Switch Bus bus. According to the transmission characteristics of each channel, the data merging, splitting control and address misalignment transmission are effectively solved by using the cache structure. The state machine centralized control method is used to realize the bridge interconnection between different transmission protocols and different bit width buses to ensure the high efficiency of data transmission. The asynchronous FIFO controller with depth of 4 is designed by using asynchronous FIFO technology. The asynchronous connection between the SRIO component and the chip system bus is realized, and the problem that the frequency of the system bus is inconsistent with the frequency of the SRIO is solved. In this paper, the bridge controller is fully simulated at module level, component level and system level, and the code coverage is calculated. The verification results show that the function of the part is correct and meets the requirements of system design. In this paper, the logic synthesis of bridge controller based on 65nmCMOS process is carried out, and the structure and timing of the design are optimized. The results show that the operating frequency of the AXI bus bridge controller can reach 500 MHz under the worst process conditions, and the expected design goal is achieved.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP332

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本文編號(hào)：2146030