【摘要】：隨著深亞微米等高科技技術(shù)的發(fā)展，存儲(chǔ)器在SoC以及所有集成電路產(chǎn)品中所占的地位變得越來(lái)越重要。存儲(chǔ)器芯片的容量變得越來(lái)越大，集成度也越來(lái)越高，使得存儲(chǔ)器內(nèi)部的晶體管以及其他部件越來(lái)越密集。正是由于存儲(chǔ)器的高布線的密度、高復(fù)雜度和高工作頻率這些因素，使得存儲(chǔ)器芯片更容易發(fā)生各種各樣的物理故障或者缺陷。存儲(chǔ)器其結(jié)構(gòu)的特殊性決定了該類(lèi)芯片不能采用傳統(tǒng)的直接物理檢測(cè)。比較可行的辦法就是對(duì)存儲(chǔ)單元的狀態(tài)進(jìn)行不斷的讀寫(xiě)，然后與正確的存儲(chǔ)單元的狀態(tài)進(jìn)行對(duì)比和比較，這樣做就可以使得故障的物理表現(xiàn)形式轉(zhuǎn)化為邏輯顯示的形式。面對(duì)越來(lái)越多的測(cè)試需求，開(kāi)發(fā)出高效的測(cè)試算法成為當(dāng)下的研究熱點(diǎn)。 本文分析了存儲(chǔ)器中常見(jiàn)的靜態(tài)和動(dòng)態(tài)故障的故障原理，并給出了測(cè)試每種故障的March元素；對(duì)于目前最為流行的幾種經(jīng)典March算法，本文著重分析了能夠覆蓋所有簡(jiǎn)單靜態(tài)故障的March SS算法的測(cè)試原理；有了以上兩點(diǎn)作為理論基礎(chǔ)，同時(shí)考慮到目前還沒(méi)有任何一種算法能夠覆蓋所有的靜態(tài)和動(dòng)態(tài)故障，本文改進(jìn)March SS算法，得到了可以覆蓋所有靜態(tài)和動(dòng)態(tài)故障的March SD算法。該算法故障覆蓋率高，測(cè)試復(fù)雜度較低，對(duì)進(jìn)一步提高芯片的良品率，，降低芯片測(cè)試時(shí)間和成本有著十分重要的意義。 為了驗(yàn)證March SD算法的測(cè)試性能和效率，本文還給出了存儲(chǔ)器測(cè)試儀的設(shè)計(jì)與實(shí)現(xiàn)，該測(cè)試儀可以適用于所有March算法的測(cè)試。整體架構(gòu)采用目前較為流行的虛擬儀器設(shè)計(jì)技術(shù)，底層采用FPGA邏輯電路來(lái)實(shí)現(xiàn)對(duì)存儲(chǔ)器芯片的矢量施加和結(jié)果返回，上位機(jī)界面采用LabVIEW圖形化編程語(yǔ)言，完成算法的解析和測(cè)試矢量生成，并直觀的顯示整個(gè)測(cè)試過(guò)程。通過(guò)該測(cè)試系統(tǒng)，可以對(duì)比各種算法的測(cè)試性能和測(cè)試效率。
[Abstract]:With the development of deep submicron and other high-tech technologies, memory plays an increasingly important role in SoC and all integrated circuit products. The capacity and integration of memory chips become larger and higher, which makes the internal transistors and other components more and more dense. Because of the high density, high complexity and high working frequency of the memory, the memory chip is prone to a variety of physical failures or defects. Because of the particularity of memory structure, this kind of chip can not use traditional direct physical detection. The more feasible method is to read and write the state of the memory cell continuously, and then compare and compare with the correct state of the memory cell. In this way, the physical representation of the fault can be transformed into the form of logical display. In the face of more and more testing requirements, the development of efficient testing algorithms has become a research hotspot. In this paper, the fault principle of the common static and dynamic faults in memory is analyzed, and the March element to test each fault is given. This paper focuses on the test principle of March SS algorithm, which can cover all simple static faults, has the above two points as the theoretical basis, and considers that none of the algorithms can cover all static and dynamic faults at present. This paper improves the March SS algorithm and obtains the March SD algorithm which can cover all static and dynamic faults. The algorithm has high fault coverage and low test complexity. It is of great significance to further improve the chip quality rate and reduce the test time and cost of the chip. In order to verify the performance and efficiency of the March SD algorithm, the design and implementation of the memory tester are presented in this paper, which can be applied to all March algorithms. The whole architecture adopts the popular virtual instrument design technology, the bottom layer adopts FPGA logic circuit to implement the vector application and the result return of the memory chip, and the upper computer interface adopts LabVIEW graphical programming language. Complete the algorithm analysis and test vector generation, and visual display of the entire test process. Through the test system, the test performance and efficiency of various algorithms can be compared.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類(lèi)號(hào)】：TP333

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本文編號(hào)：2120622