【摘要】：隨著深亞微米等高科技技術(shù)的發(fā)展，存儲器在SoC以及所有集成電路產(chǎn)品中所占的地位變得越來越重要。存儲器芯片的容量變得越來越大，集成度也越來越高，使得存儲器內(nèi)部的晶體管以及其他部件越來越密集。正是由于存儲器的高布線的密度、高復(fù)雜度和高工作頻率這些因素，使得存儲器芯片更容易發(fā)生各種各樣的物理故障或者缺陷。存儲器其結(jié)構(gòu)的特殊性決定了該類芯片不能采用傳統(tǒng)的直接物理檢測。比較可行的辦法就是對存儲單元的狀態(tài)進行不斷的讀寫，然后與正確的存儲單元的狀態(tài)進行對比和比較，這樣做就可以使得故障的物理表現(xiàn)形式轉(zhuǎn)化為邏輯顯示的形式。面對越來越多的測試需求，開發(fā)出高效的測試算法成為當(dāng)下的研究熱點。 本文分析了存儲器中常見的靜態(tài)和動態(tài)故障的故障原理，并給出了測試每種故障的March元素；對于目前最為流行的幾種經(jīng)典March算法，本文著重分析了能夠覆蓋所有簡單靜態(tài)故障的March SS算法的測試原理；有了以上兩點作為理論基礎(chǔ)，同時考慮到目前還沒有任何一種算法能夠覆蓋所有的靜態(tài)和動態(tài)故障，本文改進March SS算法，得到了可以覆蓋所有靜態(tài)和動態(tài)故障的March SD算法。該算法故障覆蓋率高，測試復(fù)雜度較低，對進一步提高芯片的良品率，，降低芯片測試時間和成本有著十分重要的意義。 為了驗證March SD算法的測試性能和效率，本文還給出了存儲器測試儀的設(shè)計與實現(xiàn)，該測試儀可以適用于所有March算法的測試。整體架構(gòu)采用目前較為流行的虛擬儀器設(shè)計技術(shù)，底層采用FPGA邏輯電路來實現(xiàn)對存儲器芯片的矢量施加和結(jié)果返回，上位機界面采用LabVIEW圖形化編程語言，完成算法的解析和測試矢量生成，并直觀的顯示整個測試過程。通過該測試系統(tǒng)，可以對比各種算法的測試性能和測試效率。
[Abstract]:With the development of deep submicron and other high-tech technologies, memory plays an increasingly important role in SoC and all integrated circuit products. The capacity and integration of memory chips become larger and higher, which makes the internal transistors and other components more and more dense. Because of the high density, high complexity and high working frequency of the memory, the memory chip is prone to a variety of physical failures or defects. Because of the particularity of memory structure, this kind of chip can not use traditional direct physical detection. The more feasible method is to read and write the state of the memory cell continuously, and then compare and compare with the correct state of the memory cell. In this way, the physical representation of the fault can be transformed into the form of logical display. In the face of more and more testing requirements, the development of efficient testing algorithms has become a research hotspot. In this paper, the fault principle of the common static and dynamic faults in memory is analyzed, and the March element to test each fault is given. This paper focuses on the test principle of March SS algorithm, which can cover all simple static faults, has the above two points as the theoretical basis, and considers that none of the algorithms can cover all static and dynamic faults at present. This paper improves the March SS algorithm and obtains the March SD algorithm which can cover all static and dynamic faults. The algorithm has high fault coverage and low test complexity. It is of great significance to further improve the chip quality rate and reduce the test time and cost of the chip. In order to verify the performance and efficiency of the March SD algorithm, the design and implementation of the memory tester are presented in this paper, which can be applied to all March algorithms. The whole architecture adopts the popular virtual instrument design technology, the bottom layer adopts FPGA logic circuit to implement the vector application and the result return of the memory chip, and the upper computer interface adopts LabVIEW graphical programming language. Complete the algorithm analysis and test vector generation, and visual display of the entire test process. Through the test system, the test performance and efficiency of various algorithms can be compared.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP333

【參考文獻】

相關(guān)期刊論文 前3條

1 許偉達;;IC測試原理-存儲器和邏輯芯片的測試[J];半導(dǎo)體技術(shù);2006年05期

2 王麗;施玉霞;王友仁;;一種嵌入式存儲器內(nèi)建自測試電路設(shè)計[J];計算機測量與控制;2008年05期

3 蘇彥鵬;薛忠杰;須自明;韓磊;;一種改進的嵌入式存儲器測試算法[J];微計算機信息;2007年02期

相關(guān)碩士學(xué)位論文 前5條

1 趙雪蓮;微控制器測試向量生成方法的研究和實現(xiàn)[D];西南交通大學(xué);2006年

2 任愛玲;嵌入式memory內(nèi)建自測試算法[D];東南大學(xué);2005年

3 姚俊;基于BIST的嵌入式存儲器可測性設(shè)計算法研究[D];哈爾濱工程大學(xué);2007年

4 程沁;嵌入式SRAM內(nèi)建自測試設(shè)計[D];西安電子科技大學(xué);2008年

5 白石;嵌入式存儲器的可測性設(shè)計及測試算法研究[D];哈爾濱工業(yè)大學(xué);2009年

本文編號：2120622