本文選題：IEEE1394 + 鏈路層IP核　； 參考：《西安電子科技大學(xué)》2015年碩士論文

【摘要】：隨著計(jì)算機(jī)技術(shù)的迅速發(fā)展,人們對總線的傳輸速度和可靠性都提出了更高的要求,IEEE1394協(xié)議作為一種高性能的串行總線技術(shù)標(biāo)準(zhǔn),因?yàn)槠渚哂畜w積小、傳輸速率高、可靠性高、支持異步數(shù)據(jù)和等時數(shù)據(jù)傳輸模式等優(yōu)點(diǎn),在家用電子、多媒體、網(wǎng)絡(luò)、存儲設(shè)備、航空航天等領(lǐng)域得到了較為廣泛的應(yīng)用。本文首先提出了一種與IEEE1394協(xié)議相適應(yīng)的鏈路層IP核的設(shè)計(jì)方法,實(shí)現(xiàn)了1394協(xié)議中規(guī)定的關(guān)于主包、物理包和響應(yīng)包三類包的發(fā)送和接收的功能。本設(shè)計(jì)中的整個IP核按照模塊劃分,主要包括發(fā)送TRANSMIT模塊、接收RECEIVE模塊、主要控制LINKSM模塊、CRC校驗(yàn)?zāi)K、PHYINT接口模塊、事物層FIFO接口模塊、寄存器INT_CTRL模塊等。為了提高發(fā)送和接收數(shù)據(jù)包的效率,本設(shè)計(jì)中的鏈路層IP核對錯誤包的發(fā)送和接收進(jìn)行了過濾。發(fā)送時,如果數(shù)據(jù)包的包頭信息出現(xiàn)錯誤,鏈路層會產(chǎn)生一個復(fù)位信號,進(jìn)而消除相應(yīng)錯誤的數(shù)據(jù)包;如果數(shù)據(jù)包的包負(fù)載信息和包頭信息不一致,鏈路層會根據(jù)包頭信息的指示對包負(fù)載進(jìn)行處理,并將處理后的數(shù)據(jù)包發(fā)送到物理層。接收時,如果數(shù)據(jù)包的包頭信息有錯誤,鏈路層會給產(chǎn)生一個錯誤包撤銷指示信號,進(jìn)而消除之前接收到的有錯誤的數(shù)據(jù)包;如果這個數(shù)據(jù)包的包負(fù)載信息有錯誤,鏈路層會將這個數(shù)據(jù)包存入事物層FIFO并產(chǎn)生一個數(shù)據(jù)包錯誤的指示信號。接著本文對IEEE1394鏈路層IP核進(jìn)行了驗(yàn)證。為了提高驗(yàn)證效率,本文使用了目前驗(yàn)證中應(yīng)用最多的通用虛擬驗(yàn)證方法學(xué)UVM。在綜合考慮驗(yàn)證工作的復(fù)雜度、驗(yàn)證工作的必要性和模擬鏈路層工作環(huán)境的充分性等因素后,提出了IEEE1394鏈路層驗(yàn)證平臺的搭建方法,并制訂了相應(yīng)的驗(yàn)證計(jì)劃。根據(jù)驗(yàn)證計(jì)劃的要求,編寫出了300多項(xiàng)相關(guān)的測試向量,完成了對鏈路層IP核中設(shè)計(jì)的異步數(shù)據(jù)包發(fā)送、異步數(shù)據(jù)包接收、等時數(shù)據(jù)包發(fā)送、等時數(shù)據(jù)包接收和錯誤數(shù)據(jù)包過濾等功能的驗(yàn)證。根據(jù)Questasim仿真器的仿真結(jié)果可以看出,本文中所設(shè)計(jì)的鏈路層IP核實(shí)現(xiàn)了1394串行總線協(xié)議中關(guān)于鏈路層部分所規(guī)定的功能和鏈路層對錯誤數(shù)據(jù)包進(jìn)行過濾的功能。最后完成了覆蓋率的相關(guān)測試,實(shí)現(xiàn)了對IEEE1394鏈路層IP核的前期驗(yàn)證的評估。
[Abstract]:With the rapid development of computer technology, more demands have been put forward for the transmission speed and reliability of the bus. IEEE1394 protocol is regarded as a high performance serial bus technical standard, because of its small volume, high transmission rate and high reliability. It supports asynchronous data and isochronous data transmission mode, and has been widely used in home electronics, multimedia, network, storage devices, aerospace and other fields. In this paper, a design method of link layer IP core adapted to IEEE1394 protocol is proposed, which realizes the function of sending and receiving three kinds of packets, including main packet, physical packet and response packet, as specified in 1394 protocol. The whole IP core in this design is divided according to the module, mainly including sending TRANSMIT module, receiving RECEIVE module, controlling LINKSM module and CRC checking module, controlling PHYINT interface module, thing layer FIFO interface module, register INTCTRL module and so on. In order to improve the efficiency of sending and receiving data packets, the link layer IP check error packets are filtered in this design. When sending, if the packet header information of the packet is wrong, the link layer will produce a reset signal, which will eliminate the corresponding error packet; if the packet load information and the packet header information are inconsistent, The link layer processes the packet load according to the header information and sends the processed packet to the physical layer. When received, if there is an error in the packet header information, the link layer generates an error packet revocation indication signal, thereby eliminating the error packet previously received; if there is an error in the packet load information of the packet, The link layer stores the packet into the transaction layer FIFO and generates an indication of the packet error. Then we verify the IEEE 1394 link layer IP core. In order to improve the efficiency of verification, this paper uses the universal virtual verification methodology (UVM), which is widely used in verification. After considering the complexity of verification, the necessity of verification and the adequacy of analog link layer working environment, this paper proposes a method to build the IEEE1394 link layer verification platform, and formulates the corresponding verification plan. According to the requirements of the verification plan, more than 300 related test vectors have been written, and the asynchronous packet transmission, asynchronous data packet reception, isochronous packet transmission in the link layer IP core have been completed. Verification of isochronous packet reception and error packet filtering. According to the simulation results of the Questasim simulator, it can be seen that the link layer IP core designed in this paper realizes the functions of the link layer part of the 1394 serial bus protocol and the link layer filtering error packets. Finally, the coverage test is completed, and the previous verification of IEEE1394 link layer IP core is realized.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TP336

【參考文獻(xiàn)】

相關(guān)期刊論文 前1條

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本文編號：2118159