發(fā)布時間：2018-07-06 12:03

  本文選題：SPM數(shù)據(jù)分配 + Cache行為分析�。� 參考：《山東大學》2014年碩士論文

【摘要】：近年來,隨著物聯(lián)網(wǎng)技術(shù)和嵌入式智能設備的增長,嵌入式系統(tǒng)得到了迅速的發(fā)展。嵌入式技術(shù)越來越多的應用到無線通訊、智能電話、醫(yī)療技術(shù)和智能樓宇等深深的影響著人們?nèi)粘Ｉ畹念I(lǐng)域和行業(yè)中。當今的嵌入式設備對嵌入式系統(tǒng)的運行效率、持續(xù)運行時間、穩(wěn)定性等都提出了更高的要求,因此在嵌入式系統(tǒng)的設計中,針對系統(tǒng)的計算性能和能耗的優(yōu)化是需要考慮的重要問題。 為了緩解CPU運算速度與內(nèi)存讀寫速度不匹配的矛盾,計算機系統(tǒng)引入了片上緩存技術(shù),而當今常用的片上靜態(tài)隨機存儲器包括片上高速緩存(Cache)和便箋式存儲器(SPM,Scratchpad Memory)已經(jīng)廣泛應用到嵌入式系統(tǒng)中。在數(shù)據(jù)密集型的程序中,內(nèi)存子系統(tǒng)是整個系統(tǒng)的性能和能耗瓶頸,在高性能和高能效嵌入式系統(tǒng)設計中,內(nèi)存子系統(tǒng)的優(yōu)化是一個關(guān)鍵的考慮因素。雖然現(xiàn)在很多嵌入式系統(tǒng)中已經(jīng)開始使用Cache和SPM作為片上RAM的混合設計,但許多現(xiàn)有SPM數(shù)據(jù)優(yōu)化算法只針對純SPM的架構(gòu),不適用于使用SPM和Cache混合存儲架構(gòu)。本文以片上SPM和Cache混合緩存架構(gòu)為背景,圍繞混合片上存儲器性能和能耗優(yōu)化這一主題,提出了基于Cache行為分析的混合片上高速存儲器SPM和Cache數(shù)據(jù)分配優(yōu)化算法。 論文的主要工作包括： (1)通過研究混合SRAM架構(gòu)下的SPM數(shù)據(jù)分配問題來優(yōu)化嵌入式系統(tǒng)性能和能耗。本文提出一種基于整數(shù)線性規(guī)劃的最優(yōu)化解決方案,方案不但考慮數(shù)據(jù)在Cache中的訪問頻率,而且考慮內(nèi)存塊在Cache中未命中時的沖突行為,最終使用整數(shù)線性規(guī)劃來求取使性能最高或能耗最低的SPM分配方案。對比純SPM的架構(gòu),實驗結(jié)果顯示本文的混合存儲器優(yōu)化算法能更好的利用片上存儲器的優(yōu)勢。 (2)提出一種基于數(shù)據(jù)Cache跟蹤的Cache行為分析模型。本文采用并擴充了時空沖突集(TCS,Temporal Conflict Set)的理論作為精確分析Cache行為的模型。該模型與基于Cache沖突圖的分析模型相比,本文模型使用TCS作為Cache分析的基礎,算法對于每一次Cache未命中計算一個詳細的沖突序列,通過ILP算法精確的計算出由于內(nèi)存塊的不同SPM分配對Cache行為造成的不同影響。 (3)為最大限度的利用SPM的優(yōu)勢,本文最后提出基于內(nèi)存塊的數(shù)組細粒度分割算法。在數(shù)組分割算法中,每個數(shù)組可以被分為多個不同的部分,有些部分會被映射到SPM中,有些被分配到外存中,這種細粒度的數(shù)組分割方法能更大程度的提高系統(tǒng)性能和降低系統(tǒng)能耗。 (4)優(yōu)化方案整合到一個統(tǒng)一編譯框架中,從ILP優(yōu)化器中優(yōu)化完的結(jié)果會被轉(zhuǎn)換成一個鏈接腳本文件,這個優(yōu)化腳本會重新被編譯器編譯成一個優(yōu)化后的執(zhí)行體。本文的工作基于改進的SimpleScalar仿真工具。
[Abstract]:In recent years, with the growth of Internet of things technology and embedded intelligent devices, embedded systems have been rapidly developed. Embedded technology is more and more used in wireless communication, smart phone, medical technology and intelligent building, which deeply affect the fields and industries of people's daily life. Nowadays, embedded devices have put forward higher requirements for the running efficiency, running time and stability of embedded system, so in the design of embedded system, The optimization of system performance and energy consumption is an important problem to be considered. In order to alleviate the contradiction between CPU operation speed and memory read / write speed, the technology of on-chip cache is introduced in computer system. Nowadays, on-chip static random access memory (SRAM), including on-chip cache (Cache) and note memory (SPM), has been widely used in embedded systems. In data-intensive programs, the memory subsystem is the bottleneck of the performance and energy consumption of the whole system, and the optimization of the memory subsystem is a key consideration in the design of high-performance and energy-efficient embedded systems. Although many embedded systems have started to use cache and SPM as the hybrid design of on-chip RAM, but many existing SPM data optimization algorithms are only for pure SPM architecture, not for the use of SPM and cache hybrid storage architecture. In this paper, the SPM and cache hybrid cache architecture is taken as the background, and the optimization algorithm of SPM and cache data allocation based on Cache behavior analysis is proposed around the optimization of memory performance and energy consumption on the hybrid chip. The main work of this paper is as follows: (1) the performance and energy consumption of embedded system are optimized by studying the SPM data allocation problem in hybrid SRAM architecture. In this paper, an optimization solution based on integer linear programming is proposed. The scheme not only considers the access frequency of data in cache, but also considers the collision behavior of memory block when it is missed in cache. Finally, integer linear programming is used to obtain the SPM allocation scheme with the highest performance or the lowest energy consumption. Compared with the pure SPM architecture, the experimental results show that the hybrid memory optimization algorithm can make better use of the advantages of on-chip memory. (2) A Cache behavior analysis model based on data cache tracking is proposed. In this paper, the theory of temporal conflict set (TCSC) is adopted and extended as a model for the accurate analysis of cache behavior. Compared with the analysis model based on cache collision graph, this model uses TCS as the basis of cache analysis, and the algorithm calculates a detailed conflict sequence for each cache miss. The ILP algorithm is used to accurately calculate the different effects of different SPM allocation on cache behavior. (3) in order to maximize the advantage of SPM, this paper proposes an array fine-grained segmentation algorithm based on memory block. In an array segmentation algorithm, each array can be divided into different parts, some of which are mapped to the SPM, some are assigned to external memory, This fine-grained array segmentation method can greatly improve system performance and reduce system energy consumption. (4) the optimization scheme is integrated into a unified compilation framework. The optimized results from the ILP optimizer are converted into a linked script file, which is recompiled by the compiler into an optimized execution. The work of this paper is based on the improved SimpleScalar simulation tool.
【學位授予單位】：山東大學
【學位級別】：碩士
【學位授予年份】：2014
【分類號】：TP333

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本文編號：2102726