本文選題：PCI + Express　； 參考：《重慶大學(xué)》2012年碩士論文

【摘要】：PCI Express(PCIE)總線作為第三代IO總線技術(shù)，因其具有傳輸帶寬高、全新的點(diǎn)點(diǎn)互連架構(gòu)和對PCI總線高度兼容等優(yōu)點(diǎn)已在計(jì)算機(jī)平臺(tái)中獲得廣泛應(yīng)用。為充分發(fā)揮PCIE總線的優(yōu)點(diǎn)，推廣PCIE總線在嵌入式系統(tǒng)等場合的應(yīng)用，本文設(shè)計(jì)了一款基于FPGA的PCIE數(shù)據(jù)傳輸系統(tǒng)，為應(yīng)用PCIE進(jìn)行數(shù)據(jù)傳輸提供了一種新的低成本方案。 本文在對PCIE協(xié)議深入研究的基礎(chǔ)上，采用自頂向下的設(shè)計(jì)思想，對PCIE數(shù)據(jù)傳輸系統(tǒng)進(jìn)行頂層設(shè)計(jì)和模塊劃分，根據(jù)PCIE IP接口完成PCIE數(shù)據(jù)傳輸系統(tǒng)應(yīng)用層的RTL級(jí)描述、仿真及驗(yàn)證，分析了其仿真和驗(yàn)證結(jié)果，，并對系統(tǒng)進(jìn)行實(shí)際測試。論文主要包括以下幾方面的內(nèi)容： 首先，對PCIE協(xié)議規(guī)范進(jìn)行全面詳細(xì)的研究，在透徹理解PCIE協(xié)議的基礎(chǔ)上，分析PCIE純粹端點(diǎn)設(shè)備的實(shí)現(xiàn)條件，選定系統(tǒng)開發(fā)平臺(tái)，按照自頂向下的設(shè)計(jì)思想，對PCIE數(shù)據(jù)傳輸系統(tǒng)進(jìn)行頂層設(shè)計(jì)和模塊劃分。 其次，利用Quartus II工具對PCIE IP進(jìn)行例化并分析IP接口，采用Verilog HDL對所劃分的PCIE IP配置模塊、PCIE應(yīng)用層輔助模塊、PCIE應(yīng)用層核心模塊進(jìn)行RTL級(jí)設(shè)計(jì)。其中PCIE IP實(shí)現(xiàn)了PCIE協(xié)議功能，通過64位Avalon-ST接口和應(yīng)用層進(jìn)行數(shù)據(jù)通信；PCIE IP配置模塊實(shí)現(xiàn)了PCIE IP配置信號(hào)采集功能和通過LMI接口配置PCIE配置空間錯(cuò)誤報(bào)告能力寄存器功能；PCIE應(yīng)用層輔助模塊實(shí)現(xiàn)了接收端口轉(zhuǎn)換、發(fā)送端口轉(zhuǎn)換、接收數(shù)據(jù)緩沖和MSI緩沖功能；應(yīng)用層核心模塊實(shí)現(xiàn)了Rc_slave和鏈?zhǔn)紻MA數(shù)據(jù)傳輸功能。論文在DMA基礎(chǔ)上實(shí)現(xiàn)了鏈?zhǔn)紻MA功能，減少了數(shù)據(jù)傳輸對CPU資源的占用，大大提高了傳輸效率。 最后，對所設(shè)計(jì)的PCIE數(shù)據(jù)傳輸系統(tǒng)整體進(jìn)行仿真測試。搭建仿真測試平臺(tái)，對系統(tǒng)整體進(jìn)行功能仿真，將綜合適配后的電路下載到FPGA中進(jìn)行時(shí)序驗(yàn)證，在PC機(jī)上利用軟件對系統(tǒng)進(jìn)行實(shí)際測試，并對相關(guān)仿真測試結(jié)果進(jìn)行分析。 基于FPGA的PCIE數(shù)據(jù)傳輸系統(tǒng)的仿真和測試結(jié)果表明，系統(tǒng)各模塊邏輯功能均達(dá)到設(shè)計(jì)要求，PCIE數(shù)據(jù)傳輸系統(tǒng)可通過Rc_slave和鏈?zhǔn)紻MA兩種模式和PC機(jī)主存儲(chǔ)器交換數(shù)據(jù)，DMA讀速度達(dá)173MB/S，DMA寫速度達(dá)207MB/S。本設(shè)計(jì)為利用低成本FPGA實(shí)現(xiàn)PCIE數(shù)據(jù)傳輸提供有效可行的實(shí)現(xiàn)方案，推廣了PCIE總線的應(yīng)用范圍，具有很好的應(yīng)用前景。
[Abstract]:PCI Express (PCIE) bus, as the third generation IO bus technology, has been widely used in computer platform because of its high transmission bandwidth, new point-point interconnection architecture and high compatibility with PCI bus. In order to give full play to the advantages of PCIE bus and extend the application of PCIE bus in embedded system, a PCIE data transmission system based on FPGA is designed in this paper, which provides a new low cost scheme for PCIE data transmission. Based on the deep research of PCIE protocol, the top layer design and module partition of PCIE data transmission system are carried out by adopting top-down design idea, and the RTL level description of PCIE data transmission system application layer is completed according to the PCIE IP interface. Simulation and verification, analysis of its simulation and verification results, and the actual test of the system. This paper mainly includes the following aspects: first, the PCIE protocol specification is studied in detail, on the basis of thorough understanding of the PCIE protocol, the realization conditions of PCIE pure endpoint equipment are analyzed, and the system development platform is selected. According to the idea of top-down design, the top-level design and module partition of PCIE data transmission system are carried out. Secondly, we use Quartus II tool to illustrate the PCIE IP and analyze the IP interface, and use Verilog HDL to design the PCIE application layer core module with Verilog HDL. The PCIE IP implements the PCIE protocol function. The PCIE IP configuration module realizes the PCIE IP configuration signal collection function and the PCIE configuration spatial error reporting capability register function through the 64-bit Avalon-St interface and the application layer data communication module. The PCIE application layer auxiliary module realizes the functions of receiving port conversion sending port conversion receiving data buffering and MSI buffering while the application layer core module realizes the functions of RC slave and chain DMA data transmission. On the basis of DMA, the paper realizes the chained DMA function, reduces the occupation of CPU resources by data transmission, and improves the transmission efficiency greatly. Finally, the PCIE data transmission system is simulated and tested. A simulation test platform is built to simulate the whole system. The integrated adapted circuit is downloaded to FPGA for timing verification. The software is used to test the system and the related simulation test results are analyzed. The simulation and test results of PCIE data transmission system based on FPGA show that, The logical functions of each module of the system can meet the design requirements. PCIE data transmission system can exchange data reading speed of 173 MB / Schi-DMA through two modes of RcServe and chain DMA and PC main memory with a speed of 207MB / s. This design provides an effective and feasible scheme for PCIE data transmission using low cost FPGA, and extends the application range of PCIE bus, and has a good application prospect.
【學(xué)位授予單位】：重慶大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP336

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