本文選題：Nand + flash存儲(chǔ)器�。� 參考：《中南大學(xué)》2013年碩士論文

【摘要】：根據(jù)NAND flash存儲(chǔ)器的特點(diǎn)與性能,推導(dǎo)出了NAND flash存儲(chǔ)器的糾錯(cuò)系統(tǒng)參數(shù)設(shè)計(jì)的方法。針對(duì)NAND flash存儲(chǔ)器,設(shè)計(jì)了一種模式可配置的糾錯(cuò)系統(tǒng)的電路結(jié)構(gòu),該結(jié)構(gòu)可以預(yù)防錯(cuò)誤位數(shù)大于設(shè)計(jì)糾錯(cuò)位數(shù)的情況發(fā)生。在傳統(tǒng)串行BCH編譯碼算法電路設(shè)計(jì)方法的基礎(chǔ)上,導(dǎo)出8位并行的BCH編譯碼算法電路設(shè)計(jì)方法。提出了一種高速并行BCH編譯碼的電路設(shè)計(jì)方法,并導(dǎo)出一種無需有限域求逆運(yùn)算的BM迭代算法的硬件實(shí)現(xiàn)方法。通過對(duì)求解有限域方程模塊復(fù)用的方法,同時(shí)結(jié)合流水線技術(shù)與乒乓操作技術(shù),巧妙的實(shí)現(xiàn)以較小的硬件邏輯資源開銷獲得糾錯(cuò)系統(tǒng)性能的提高。完成電路功能設(shè)計(jì)后,使用Modelsim軟件對(duì)糾錯(cuò)系統(tǒng)電路進(jìn)行了詳細(xì)的功能仿真分析。對(duì)糾錯(cuò)系統(tǒng)電路進(jìn)行了功耗估計(jì)分析,并采取了一定的優(yōu)化設(shè)計(jì)方法降低電路的整體功耗。該糾錯(cuò)系統(tǒng)電路已在Altera公司的EP4CE15E22C8系列FPGA芯片上實(shí)現(xiàn),并進(jìn)行了測(cè)試分析,測(cè)試結(jié)果表明,在相同的系統(tǒng)工作頻率下,該糾錯(cuò)系統(tǒng)電路的數(shù)據(jù)吞吐率是傳統(tǒng)串行糾錯(cuò)電路的八倍,而硬件邏輯資源開銷只增加了一倍。不同于傳統(tǒng)的NAND flash糾錯(cuò)電路,該糾錯(cuò)電路結(jié)構(gòu)相對(duì)獨(dú)立,可移植性強(qiáng),可滿足多種應(yīng)用場(chǎng)合的需要。圖46幅,表4個(gè),參考文獻(xiàn)61篇。
[Abstract]:According to the characteristics and performance of NAND flash memory, the design method of error correction system parameters of NAND flash memory is deduced. For NAND flash memory, a mode configurable circuit structure of error-correcting system is designed, which can prevent the occurrence of the error bit number larger than the designed error correction bit number. Based on the traditional circuit design method of serial BCH encoding and decoding algorithm, an 8-bit parallel circuit design method for BCH encoding and decoding algorithm is derived. A high speed parallel BCH encoding and decoding circuit design method is proposed, and a hardware implementation method of BM iterative algorithm without finite field inversion is derived. By using the module reuse method to solve the finite field equations and combining the pipeline technology with the ping-pong operation technology, the performance of the error correction system can be improved with less hardware logic resource overhead. After completing the circuit function design, the function simulation analysis of error correction system circuit is carried out with Modelsim software. The power estimation analysis of error correction system circuit is carried out, and a certain optimal design method is adopted to reduce the overall power consumption of the circuit. The error correction system circuit has been implemented on EP4CE15E22C8 series FPGA chip of Altera Company, and has been tested and analyzed. The test results show that under the same operating frequency, the data throughput of this error correction system circuit is eight times that of the traditional serial error correction circuit. The cost of hardware logic resources has only doubled. Different from the traditional NAND flash error correction circuit, the structure of the circuit is relatively independent and portability, which can meet the needs of many applications. 46 figures, 4 tables, 61 references.
【學(xué)位授予單位】：中南大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP333

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